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Message-Id: <1519840432-61489-1-git-send-email-giulio.benetti@micronovasrl.com>
Date:   Wed, 28 Feb 2018 18:53:51 +0100
From:   Giulio Benetti <giulio.benetti@...ronovasrl.com>
To:     Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc:     David Airlie <airlied@...ux.ie>, Chen-Yu Tsai <wens@...e.org>,
        dri-devel@...ts.freedesktop.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Giulio Benetti <giulio.benetti@...ronovasrl.com>
Subject: [PATCH 1/2] drm/sun4i: increase lvds dclk max divisor

At the moment both min and max dclk div are set to 7.
This doesn't allow to have lower frequencies.

Increase dclk_max_div to 18 to achieve 30Mhz.

Signed-off-by: Giulio Benetti <giulio.benetti@...ronovasrl.com>
---
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 029d2ce..bb35f41 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -278,7 +278,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
 	u32 reg, val = 0;
 
 	tcon->dclk_min_div = 7;
-	tcon->dclk_max_div = 7;
+	tcon->dclk_max_div = 18;
 	sun4i_tcon0_mode_set_common(tcon, mode);
 
 	/* Adjust clock delay */
-- 
2.7.4

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