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Message-ID: <20180228212417.GM127842@bhelgaas-glaptop.roam.corp.google.com>
Date: Wed, 28 Feb 2018 15:24:17 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Sinan Kaya <okaya@...eaurora.org>
Cc: linux-pci@...r.kernel.org, timur@...eaurora.org,
Kees Cook <keescook@...omium.org>,
Ard Biesheuvel <ard.biesheuvel@...aro.org>,
linux-arm-msm@...r.kernel.org,
open list <linux-kernel@...r.kernel.org>,
Vidya Sagar <vidyas@...dia.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rajat Jain <rajatja@...gle.com>,
Yinghai Lu <yinghai@...nel.org>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH V2] PCI/ASPM: Suppress common clock mode setting failure
On Mon, Jan 22, 2018 at 03:12:01PM -0500, Sinan Kaya wrote:
> Code is emitting warnings when it tries to set the common clock mode for
> ASPM and ASPM is already configured to common clock mode by the UEFI BIOS.
> Let's bail out silently in such a case.
>
> pci 0004:00:00.0: ASPM: Could not configure common clock
>
> Signed-off-by: Sinan Kaya <okaya@...eaurora.org>
Applied to pci/aspm for v4.17, thanks!
> ---
> drivers/pci/pcie/aspm.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 9783e10..913b90d 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -240,6 +240,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
> if (!(reg16 & PCI_EXP_LNKSTA_SLC))
> same_clock = 0;
>
> + /* Port might be already in common clock mode */
> + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
> + if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
> + bool consistent = true;
> +
> + list_for_each_entry(child, &linkbus->devices, bus_list) {
> + pcie_capability_read_word(child, PCI_EXP_LNKCTL,
> + ®16);
> + if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
> + consistent = false;
> + break;
> + }
> + }
> + if (consistent)
> + return;
> + dev_warn(&parent->dev, "ASPM: current common clock configuration is broken, reconfiguring\n");
> + }
> +
> /* Configure downstream component, all functions */
> list_for_each_entry(child, &linkbus->devices, bus_list) {
> pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
> --
> 1.9.1
>
>
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