linux-kernel - Re: Possible usb_request leak in the function dwc2_gadget_complete_isoc_request

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Message-ID: <410670D7E743164D87FA6160E7907A560113A9C13B@am04wembxb.internal.synopsys.com>
Date:   Wed, 28 Feb 2018 10:27:14 +0000
From:   Minas Harutyunyan <Minas.Harutyunyan@...opsys.com>
To:     "Zengtao (B)" <prime.zeng@...ilicon.com>,
        "johnyoun@...opsys.com" <John.Youn@...opsys.com>
CC:     "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: Possible usb_request leak in the function
 dwc2_gadget_complete_isoc_request_ddma

Hi,

On 2/28/2018 1:00 PM, Zengtao (B) wrote:
> Hi johnyoun:
> 
> I found a suspected bug, and I am writing to confirm with you.
> 
> In the function dwc2_gadget_complete_isoc_request_ddma(drivers/usb/dwc2/gadget.c).
> Only the first request from the eq queue is processed while maybe there are more than one descriptors done by the HW.
> 
> 1. Each usb request is associated with a DMA descriptor, but this is not reflect in the driver, so when one DMA descriptor is done,
> we don't know which usb request is done, but I think if only one DMA descriptor is done, we can know that the first USB request in
> eq queue is done, because the HW DMA descriptor and SW usb request are both in sequence.
> 
> 2. In the function dwc2_gadget_complete_isoc_request_ddma, we may complete more than one DMA descriptor but only the first
> Usb request is processed, but in fact, we should all the usb requests associated with all the done DMA descriptors.
> 
> 3. I noticed that each DMA descriptor is configured to report an interrupt, and if each DMA descriptor generate an interrupt, the above
> Flow should be ok, but the interrupts can merge and we have used the depdma to figure out the largest finished DMA descriptor index.
> 

Why you suspect that subsequent interrupts can be merged? Did you see 
this case? Can you provide a log?
Even in case of minimal interval=1, time between 2 subsequent interrupts 
should be about 125us. It's fully enough to process target descriptor, 
complete request, enqueue new request and prepare new descriptor.

Thanks,
Minas

> Looking forward your reply.
> 
> Thank you.
> 
> Regards
> Zengtao
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