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Date:   Fri, 2 Mar 2018 12:11:48 +0800
From:   David Wang <davidwang@...oxin.com>
To:     <rjw@...ysocki.net>, <len.brown@...el.com>, <pavel@....cz>,
        <tglx@...utronix.de>, <mingo@...hat.com>, <hpa@...or.com>,
        <x86@...nel.org>, <linux-pm@...nel.org>,
        <linux-kernel@...r.kernel.org>
CC:     <brucechang@...-alliance.com>, <cooperyan@...oxin.com>,
        <qiyuanwang@...oxin.com>, <benjaminpan@...tech.com>,
        <lukelin@...cpu.com>, <timguo@...oxin.com>, <cobechen@...oxin.com>,
        <jiangbowang@...oxin.com>, David Wang <davidwang@...oxin.com>
Subject: [PATCH] Delete some unusefull operations for centaur CPU/platform

For Centaur CPU, the ucode will make sure that each CPU core can keep cache
coherency with each other when the CPU core entering to any C state. So the
cache flush operations when enter C3 is not necessary and will cause large
C3 enter/exit latency.
And the bus master disable operation when CPU core entering C3 state is not
needed too. Because the chipset will automatically do this operation.

Signed-off-by: David Wang <davidwang@...oxin.com>
---
 arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index dde437f..1cd357b 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
 	if (c->x86_vendor == X86_VENDOR_INTEL &&
 	    (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
 			flags->bm_control = 0;
+
+        if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+		/*
+		 * on all centaur CPUs, sw need not execute cache flush operation
+		 * when entering C3 type State.
+		 *
+		 * On all Centaur platforms, sw need not execute ARB_DISABLE while
+		 * entering C3 type state.
+		 */
+		flags->bm_check = 1;
+		flags->bm_control = 0;
+	}
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
-- 
1.9.1

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