linux-kernel - Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS SoCs

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Date:   Fri, 2 Mar 2018 16:22:24 +0100
From:   Alexandre Belloni <alexandre.belloni@...e-electrons.com>
To:     James Hogan <jhogan@...nel.org>
Cc:     Paul Burton <paul.burton@...s.com>,
        Ralf Baechle <ralf@...ux-mips.org>, linux-mips@...ux-mips.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 09/13] MIPS: mscc: Add initial support for Microsemi MIPS
 SoCs

Hi,

On 17/01/2018 at 23:58:47 +0000, James Hogan wrote:
> Poking at random I/O always feels a bit risky.
> 
> Some safety checked environment checking (Paul says modetty0 should
> always be in there for YAMON) might work.
> 
> Does Ocelot have a read-only ID register with a specific value? We'd
> have to add prioritisation of the legacy board detection to rely on
> that.
> 

There is an ID register at 0x71070000.

> If all else fails, we could still make them mutually exclusive,
> something roughly like below would work but its a bit clumsy as all the
> ocelot config options would still get enabled when sead3 is enabled,
> even though some of the drivers may not be useful. The detection &
> co-existence can always be improved later. What do you think?
> 

I now have something working based on what you suggested. I'm cleaning
that up and I'll resubmit soon.


-- 
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com