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Message-Id: <1520274210-21748-1-git-send-email-parri.andrea@gmail.com>
Date: Mon, 5 Mar 2018 19:23:30 +0100
From: Andrea Parri <parri.andrea@...il.com>
To: Palmer Dabbelt <palmer@...ive.com>, Albert Ou <albert@...ive.com>
Cc: Daniel Lustig <dlustig@...dia.com>,
Alan Stern <stern@...land.harvard.edu>,
Will Deacon <will.deacon@....com>,
Peter Zijlstra <peterz@...radead.org>,
Boqun Feng <boqun.feng@...il.com>,
Nicholas Piggin <npiggin@...il.com>,
David Howells <dhowells@...hat.com>,
Jade Alglave <j.alglave@....ac.uk>,
Luc Maranget <luc.maranget@...ia.fr>,
Paul McKenney <paulmck@...ux.vnet.ibm.com>,
Akira Yokosawa <akiyks@...il.com>,
Ingo Molnar <mingo@...nel.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Andrea Parri <parri.andrea@...il.com>
Subject: [RFC PATCH 0/2] riscv/spinlock,atomic: Miscellaneous fixes
Hi,
This RFC is a follow-up on the discussion in [1], which led to the
discovery of a few issues in the current implementations of RISC-V
locking and atomic operations.
In summary, this series proposes the following modifications:
1. Use lightweigth fences for acquire/release (locking, atomics)
2. Use the combination of .rl and full fences for fully-ordered
atomics implemented with LR/SC pairs.
3. A few style changes (80-chars lines, alignment).
Applies on top of "next-smp_sl_ar".
Cheers,
Andrea
[1] https://marc.info/?l=linux-kernel&m=151930201102853&w=2
Andrea Parri (2):
riscv/spinlock: Strengthen implementations with fences
riscv/atomic: Strengthen implementations with fences
arch/riscv/include/asm/atomic.h | 417 ++++++++++++++++++++++++--------------
arch/riscv/include/asm/cmpxchg.h | 391 ++++++++++++++++++++++++++++-------
arch/riscv/include/asm/fence.h | 12 ++
arch/riscv/include/asm/spinlock.h | 29 +--
4 files changed, 615 insertions(+), 234 deletions(-)
create mode 100644 arch/riscv/include/asm/fence.h
--
2.7.4
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