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Message-ID: <CAGS+omCr2YUcAmv9068kR1s4LOqCGij_ps3+9tQ92whVWvGBxg@mail.gmail.com>
Date:   Wed, 07 Mar 2018 23:30:11 +0000
From:   Daniel Kurtz <djkurtz@...omium.org>
To:     Daniel Kurtz <djkurtz@...omium.org>
Cc:     adurbin@...omium.org, Brian Norris <briannorris@...omium.org>,
        Jonathan Corbet <corbet@....net>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        jslaby@...e.com, mingo@...nel.org,
        Thomas Gleixner <tglx@...utronix.de>,
        Christoffer Dall <cdall@...aro.org>,
        Paul McKenney <paulmck@...ux.vnet.ibm.com>,
        marc.zyngier@....com, frederic@...nel.org, dwmw@...zon.co.uk,
        tom.saeger@...cle.com, zohar@...ux.vnet.ibm.com,
        alexander.levin@...izon.com, linux-doc@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v2] earlycon: Allow specifying a uartclk in options

On Thu, Mar 1, 2018 at 11:43 AM Daniel Kurtz <djkurtz@...omium.org> wrote:

> Currently when an earlycon is registered, the uartclk is assumed to be
> BASE_BAUD * 16 = 1843200.  If a baud rate is specified in the earlycon
> options, then 8250_early's init_port will program the UART clock divider
> registers based on this assumed uartclk.

> However, not all uarts have a UART clock of 1843200.  For example, the
> 8250_dw uart in AMD's CZ/ST uses a fixed 48 MHz clock (as specified in
> cz_uart_desc in acpi_apd.c).  Thus, specifying a baud when using earlycon
> on such a device will result in incorrect divider values and a wrong UART
> clock.

> Fix this by extending the earlycon options parameter to allow
specification
> of a uartclk, like so:

>   earlycon=uart,mmio32,0xfedc6000,115200,48000000

> If none is specified, fall-back to prior behavior - 1843200.

> Signed-off-by: Daniel Kurtz <djkurtz@...omium.org>

This general approach is facing resistance, so trying another more targeted
approach to work around the "BASE_BAUD=115200" assumption in arch/x86:

https://patchwork.kernel.org/patch/10265587/

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