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Message-ID: <20180308141501.GH3529@ulmo>
Date: Thu, 8 Mar 2018 15:15:01 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Marcel Ziswiler <marcel@...wiler.com>
Cc: linux-tegra@...r.kernel.org, devicetree@...r.kernel.org,
Dmitry Osipenko <digetx@...il.com>,
Marcel Ziswiler <marcel.ziswiler@...adex.com>,
Jonathan Hunter <jonathanh@...dia.com>,
linux-kernel@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Russell King <linux@...linux.org.uk>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2] ARM: tegra: fix ulpi regression on tegra20
On Thu, Feb 22, 2018 at 03:38:25PM +0100, Marcel Ziswiler wrote:
> From: Marcel Ziswiler <marcel.ziswiler@...adex.com>
>
> Since commit f8f8f1d04494 ("clk: Don't touch hardware when reparenting
> during registration") ULPI has been broken on Tegra20 leading to the
> following error message during boot:
>
> [ 1.974698] ulpi_phy_power_on: ulpi write failed
> [ 1.979384] tegra-ehci c5004000.usb: Failed to power on the phy
> [ 1.985434] tegra-ehci: probe of c5004000.usb failed with error -110
>
> Debugging through the changes and finally also consulting the TRM
> revealed that rather than the CDEV2 clock off OSC requiring such pin
> muxing actually the PLL_P_OUT4 clock is in use. It looks like so far it
> just worked by chance of that one having been enabled which Stephen's
> commit now changed when reparenting sclk away from pll_p_out4 leaving
> that one disabled. Fix this by properly assigning the PLL_P_OUT4 clock
> as the ULPI PHY clock.
>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
>
> ---
>
> Changes in v2:
> - Updated device tree binding documentation as well.
> - CCing Dmitry as well.
>
> Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt | 4 +++-
> arch/arm/boot/dts/tegra20.dtsi | 2 +-
> 2 files changed, 4 insertions(+), 2 deletions(-)
Applied, though I've split this into two separate patches, one going
into for-4.17/dt-bindings and the other going into for-4.17/arm/dt.
Thanks,
Thierry
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