linux-kernel - [tip:ras/urgent] x86/MCE: Save microcode revision in machine check records

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Message-ID: <tip-fa94d0c6e0f3431523f5701084d799c77c7d4a4f@git.kernel.org>
Date:   Thu, 8 Mar 2018 06:39:52 -0800
From:   tip-bot for Tony Luck <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, yazen.ghannam@....com,
        mingo@...nel.org, linux-edac@...r.kernel.org, tony.luck@...el.com,
        bp@...e.de, hpa@...or.com, tglx@...utronix.de
Subject: [tip:ras/urgent] x86/MCE: Save microcode revision in machine check
 records

Commit-ID:  fa94d0c6e0f3431523f5701084d799c77c7d4a4f
Gitweb:     https://git.kernel.org/tip/fa94d0c6e0f3431523f5701084d799c77c7d4a4f
Author:     Tony Luck <tony.luck@...el.com>
AuthorDate: Tue, 6 Mar 2018 15:21:41 +0100
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Thu, 8 Mar 2018 15:34:49 +0100

x86/MCE: Save microcode revision in machine check records

Updating microcode used to be relatively rare. Now that it has become
more common we should save the microcode version in a machine check
record to make sure that those people looking at the error have this
important information bundled with the rest of the logged information.

[ Borislav: Simplify a bit. ]

Signed-off-by: Tony Luck <tony.luck@...el.com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: Yazen Ghannam <yazen.ghannam@....com>
Cc: linux-edac <linux-edac@...r.kernel.org>
Cc: stable@...r.kernel.org
Link: http://lkml.kernel.org/r/20180301233449.24311-1-tony.luck@intel.com
---
 arch/x86/include/uapi/asm/mce.h  | 1 +
 arch/x86/kernel/cpu/mcheck/mce.c | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mce.h
index 91723461dc1f..435db58a7bad 100644
--- a/arch/x86/include/uapi/asm/mce.h
+++ b/arch/x86/include/uapi/asm/mce.h
@@ -30,6 +30,7 @@ struct mce {
 	__u64 synd;	/* MCA_SYND MSR: only valid on SMCA systems */
 	__u64 ipid;	/* MCA_IPID MSR: only valid on SMCA systems */
 	__u64 ppin;	/* Protected Processor Inventory Number */
+	__u32 microcode;/* Microcode revision */
 };
 
 #define MCE_GET_RECORD_LEN   _IOR('M', 1, int)
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 8ff94d1e2dce..b3323cab9139 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -130,6 +130,8 @@ void mce_setup(struct mce *m)
 
 	if (this_cpu_has(X86_FEATURE_INTEL_PPIN))
 		rdmsrl(MSR_PPIN, m->ppin);
+
+	m->microcode = boot_cpu_data.microcode;
 }
 
 DEFINE_PER_CPU(struct mce, injectm);
@@ -262,7 +264,7 @@ static void __print_mce(struct mce *m)
 	 */
 	pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
 		m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
-		cpu_data(m->extcpu).microcode);
+		m->microcode);
 }
 
 static void print_mce(struct mce *m)