[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1520506716-197429-10-git-send-email-john.garry@huawei.com>
Date: Thu, 8 Mar 2018 18:58:34 +0800
From: John Garry <john.garry@...wei.com>
To: <jolsa@...hat.com>, <ak@...ux.intel.com>, <peterz@...radead.org>,
<mingo@...hat.com>, <acme@...nel.org>,
<alexander.shishkin@...ux.intel.com>, <namhyung@...nel.org>,
<wcohen@...hat.com>, <will.deacon@....com>,
<ganapatrao.kulkarni@...ium.com>
CC: <linuxarm@...wei.com>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<zhangshaokun@...ilicon.com>, "John Garry" <john.garry@...wei.com>
Subject: [PATCH v3 09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events
This patch fixes the Cavium ThunderX2 JSON to use event definitions
from the ARMv8 recommended events.
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@...ium.com>
Signed-off-by: John Garry <john.garry@...wei.com>
---
.../arch/arm64/cavium/thunderx2/core-imp-def.json | 50 +++++-----------------
1 file changed, 10 insertions(+), 40 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index 2db45c4..bc03c06 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -1,62 +1,32 @@
[
{
- "PublicDescription": "Attributable Level 1 data cache access, read",
- "EventCode": "0x40",
- "EventName": "l1d_cache_rd",
- "BriefDescription": "L1D cache read",
+ "ArchStdEvent": "L1D_CACHE_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache access, write ",
- "EventCode": "0x41",
- "EventName": "l1d_cache_wr",
- "BriefDescription": "L1D cache write",
+ "ArchStdEvent": "L1D_CACHE_WR",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, read",
- "EventCode": "0x42",
- "EventName": "l1d_cache_refill_rd",
- "BriefDescription": "L1D cache refill read",
+ "ArchStdEvent": "L1D_CACHE_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data cache refill, write",
- "EventCode": "0x43",
- "EventName": "l1d_cache_refill_wr",
- "BriefDescription": "L1D refill write",
+ "ArchStdEvent": "L1D_CACHE_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, read",
- "EventCode": "0x4C",
- "EventName": "l1d_tlb_refill_rd",
- "BriefDescription": "L1D tlb refill read",
+ "ArchStdEvent": "L1D_TLB_REFILL_RD",
},
{
- "PublicDescription": "Attributable Level 1 data TLB refill, write",
- "EventCode": "0x4D",
- "EventName": "l1d_tlb_refill_wr",
- "BriefDescription": "L1D tlb refill write",
+ "ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
- "EventCode": "0x4E",
- "EventName": "l1d_tlb_rd",
- "BriefDescription": "L1D tlb read",
+ "ArchStdEvent": "L1D_TLB_RD",
},
{
- "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
- "EventCode": "0x4F",
- "EventName": "l1d_tlb_wr",
- "BriefDescription": "L1D tlb write",
+ "ArchStdEvent": "L1D_TLB_WR",
},
{
- "PublicDescription": "Bus access read",
- "EventCode": "0x60",
- "EventName": "bus_access_rd",
- "BriefDescription": "Bus access read",
+ "ArchStdEvent": "BUS_ACCESS_RD",
},
{
- "PublicDescription": "Bus access write",
- "EventCode": "0x61",
- "EventName": "bus_access_wr",
- "BriefDescription": "Bus access write",
+ "ArchStdEvent": "BUS_ACCESS_WR",
}
]
--
1.9.1
Powered by blists - more mailing lists