linux-kernel - Re: [PATCH 1/2] watchdog: dw: RMW the control register

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Message-ID: <CA+ASDXPmh7Ng8x1dnezs5a9zSdvVVTa4W+KQYVLDWWoKW0S=-w@mail.gmail.com>
Date:   Fri, 9 Mar 2018 18:47:47 -0800
From:   Brian Norris <briannorris@...omium.org>
To:     Wim Van Sebroeck <wim@...ux-watchdog.org>,
        Guenter Roeck <linux@...ck-us.net>
Cc:     Linux Kernel <linux-kernel@...r.kernel.org>,
        linux-watchdog@...r.kernel.org,
        Doug Anderson <dianders@...omium.org>,
        Matthias Kaehlcke <mka@...omium.org>,
        Brian Norris <briannorris@...omium.org>,
        "open list:ARM/Rockchip SoC..." <linux-rockchip@...ts.infradead.org>
Subject: Re: [PATCH 1/2] watchdog: dw: RMW the control register

+ linux-rockchip (probably should have included in the first place)

On Fri, Mar 9, 2018 at 6:44 PM, Brian Norris <briannorris@...omium.org> wrote:
> RK3399 has rst_pulse_length in CONTROL_REG[4:2], determining the length
> of pulse to issue for system reset. We shouldn't clobber this value,
> because that might make the system reset ineffective. On RK3399, we're
> seeing that a value of 000b (meaning 2 cycles) yields an unreliable
> (partial?) reset, and so we only fully reset after the watchdog fires a
> second time. If we retain the system default (010b, or 8 clock cycles),
> then the watchdog reset is much more reliable.
>
> Read-modify-write retains the system value and improves reset
> reliability.
>
> Signed-off-by: Brian Norris <briannorris@...omium.org>
> ---
>  drivers/watchdog/dw_wdt.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c
> index c2f4ff516230..6925d3e6c6b3 100644
> --- a/drivers/watchdog/dw_wdt.c
> +++ b/drivers/watchdog/dw_wdt.c
> @@ -34,6 +34,7 @@
>
>  #define WDOG_CONTROL_REG_OFFSET                    0x00
>  #define WDOG_CONTROL_REG_WDT_EN_MASK       0x01
> +#define WDOG_CONTROL_REG_RESP_MODE_MASK            0x02
>  #define WDOG_TIMEOUT_RANGE_REG_OFFSET      0x04
>  #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT    4
>  #define WDOG_CURRENT_COUNT_REG_OFFSET      0x08
> @@ -124,11 +125,16 @@ static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
>  static int dw_wdt_start(struct watchdog_device *wdd)
>  {
>         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
> +       u32 val;
>
>         dw_wdt_set_timeout(wdd, wdd->timeout);
>
> -       writel(WDOG_CONTROL_REG_WDT_EN_MASK,
> -              dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
> +       val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
> +       /* Disable interrupt mode; always perform system reset. */
> +       val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
> +       /* Enable watchdog. */
> +       val |= WDOG_CONTROL_REG_WDT_EN_MASK;
> +       writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
>
>         return 0;
>  }
> --
> 2.16.2.660.g709887971b-goog
>