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Message-ID: <cea7b0bf-fcd9-6405-c437-d3251e7bb4bf@gmail.com>
Date: Mon, 12 Mar 2018 10:40:28 +0100
From: Matthias Brugger <matthias.bgg@...il.com>
To: sean.wang@...iatek.com, robh+dt@...nel.org, mark.rutland@....com,
devicetree@...r.kernel.org, linux-mediatek@...ts.infradead.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 05/19] arm: dts: mt7623: add BTIF, HSDMA and SPI-NOR
device nodes
On 02/23/2018 11:16 AM, sean.wang@...iatek.com wrote:
> From: Sean Wang <sean.wang@...iatek.com>
>
> add BTIF, HSDMA and SPI-NOR device nodes and enable it on relevant boards
AFAIK hsdma controller is not upstream yet.
Please resubmit when at least the binding got merged.
Thanks,
Matthias
>
> Signed-off-by: Sean Wang <sean.wang@...iatek.com>
> ---
> arch/arm/boot/dts/mt7623.dtsi | 36 ++++++++++++++++++++++++++-
> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 6 ++++-
> 2 files changed, 40 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index 91317a1..da56c54 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2017 MediaTek Inc.
> + * Copyright (c) 2017-2018 MediaTek Inc.
> * Author: John Crispin <john@...ozen.org>
> * Sean Wang <sean.wang@...iatek.com>
> *
> @@ -483,6 +483,18 @@
> nvmem-cell-names = "calibration-data";
> };
>
> + btif: serial@...0c000 {
> + compatible = "mediatek,mt7623-btif",
> + "mediatek,mtk-btif";
> + reg = <0 0x1100c000 0 0x1000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&pericfg CLK_PERI_BTIF>;
> + clock-names = "main";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> nandc: nfi@...0d000 {
> compatible = "mediatek,mt7623-nfc",
> "mediatek,mt2701-nfc";
> @@ -508,6 +520,18 @@
> status = "disabled";
> };
>
> + nor_flash: spi@...14000 {
> + compatible = "mediatek,mt7623-nor",
> + "mediatek,mt8173-nor";
> + reg = <0 0x11014000 0 0x1000>;
> + clocks = <&pericfg CLK_PERI_FLASH>,
> + <&topckgen CLK_TOP_FLASH_SEL>;
> + clock-names = "spi", "sf";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> spi1: spi@...16000 {
> compatible = "mediatek,mt7623-spi",
> "mediatek,mt2701-spi";
> @@ -861,6 +885,16 @@
> #reset-cells = <1>;
> };
>
> + hsdma: dma-controller@...07000 {
> + compatible = "mediatek,mt7623-hsdma";
> + reg = <0 0x1b007000 0 0x1000>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <ðsys CLK_ETHSYS_HSDMA>;
> + clock-names = "hsdma";
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
> + #dma-cells = <1>;
> + };
> +
> eth: ethernet@...00000 {
> compatible = "mediatek,mt7623-eth",
> "mediatek,mt2701-eth",
> diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> index 3efecc5..ec11e14 100644
> --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
> @@ -1,5 +1,5 @@
> /*
> - * Copyright 2017 Sean Wang <sean.wang@...iatek.com>
> + * Copyright 2017-2018 Sean Wang <sean.wang@...iatek.com>
> *
> * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> */
> @@ -86,6 +86,10 @@
> };
> };
>
> +&btif {
> + status = "okay";
> +};
> +
> &cir {
> pinctrl-names = "default";
> pinctrl-0 = <&cir_pins_a>;
>
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