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Message-ID: <CAP6Zq1ioO6cGgEnH6niuYK0zP+aW05ykKUtkn8ckUKJvriu5wg@mail.gmail.com>
Date: Mon, 12 Mar 2018 17:23:08 +0200
From: Tomer Maimon <tmaimon77@...il.com>
To: Brendan Higgins <brendanhiggins@...gle.com>
Cc: Rob Herring <robh+dt@...nel.org>,
Russell King - ARM Linux <linux@...linux.org.uk>,
Mark Rutland <mark.rutland@....com>,
Avi Fishman <avifishman70@...il.com>, julien.thierry@....com,
pombredanne@...b.com, Arnd Bergmann <arnd@...db.de>,
olof@...om.net, khilman@...nel.org,
devicetree <devicetree@...r.kernel.org>,
OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v11 2/3] arm: dts: add Nuvoton NPCM750 device tree
On 16 February 2018 at 04:40, Brendan Higgins <brendanhiggins@...gle.com> wrote:
> Add a common device tree for all Nuvoton NPCM750 BMCs and a board
> specific device tree for the NPCM750 (Poleg) evaluation board.
>
> Signed-off-by: Brendan Higgins <brendanhiggins@...gle.com>
> Reviewed-by: Tomer Maimon <tmaimon77@...il.com>
> Reviewed-by: Avi Fishman <avifishman70@...il.com>
> Reviewed-by: Joel Stanley <joel@....id.au>
> Reviewed-by: Rob Herring <robh@...nel.org>
> Tested-by: Tomer Maimon <tmaimon77@...il.com>
> Tested-by: Avi Fishman <avifishman70@...il.com>
> Tested-by: Joel Stanley <joel@....id.au>
> ---
> .../arm/cpu-enable-method/nuvoton,npcm750-smp | 42 +++++
> .../devicetree/bindings/arm/npcm/npcm.txt | 6 +
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 35 ++++
> arch/arm/boot/dts/nuvoton-npcm750.dtsi | 165 ++++++++++++++++++
> 5 files changed, 250 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
> create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt
> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
> new file mode 100644
> index 000000000000..8e043301e28e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp
> @@ -0,0 +1,42 @@
Rob,
if will like to add new chip to enable the SMP (NPCM730).
what will be the best way to add it to the binding documentation file?
1. Do I need to add new binding file nuvoton,npcm730-smp?
2. Add nuvoton,npcm730-smp option to the current nuvoton,npcm750-smp file?
3. Modify the nuvoton,npcm750-smp binding name to nuvoton,npcm7xx-smp
and to describe both chips in it.
> +=========================================================
> +Secondary CPU enable-method "nuvoton,npcm750-smp" binding
> +=========================================================
> +
> +To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be
> +defined in the "cpus" node.
> +
> +Enable method name: "nuvoton,npcm750-smp"
> +Compatible machines: "nuvoton,npcm750"
> +Compatible CPUs: "arm,cortex-a9"
> +Related properties: (none)
> +
> +Note:
> +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
> +"nuvoton,npcm750-gcr".
> +
> +Example:
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "nuvoton,npcm750-smp";
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + clocks = <&clk NPCM7XX_CLK_CPU>;
> + clock-names = "clk_cpu";
> + reg = <0>;
> + next-level-cache = <&L2>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + clocks = <&clk NPCM7XX_CLK_CPU>;
> + clock-names = "clk_cpu";
> + reg = <1>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
> new file mode 100644
> index 000000000000..2d87d9ecea85
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt
> @@ -0,0 +1,6 @@
> +NPCM Platforms Device Tree Bindings
> +-----------------------------------
> +NPCM750 SoC
> +Required root node properties:
> + - compatible = "nuvoton,npcm750";
> +
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ade7a38543dc..eeab5dac50ab 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -304,6 +304,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \
> dtb-$(CONFIG_ARCH_LPC32XX) += \
> lpc3250-ea3250.dtb \
> lpc3250-phy3250.dtb
> +dtb-$(CONFIG_ARCH_NPCM750) += \
> + nuvoton-npcm750-evb.dtb
> dtb-$(CONFIG_MACH_MESON6) += \
> meson6-atv1200.dtb
> dtb-$(CONFIG_MACH_MESON8) += \
> diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> new file mode 100644
> index 000000000000..cabde3d5be8a
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018 Nuvoton Technology corporation.
> +// Copyright 2018 Google, Inc.
> +
> +/dts-v1/;
> +#include "nuvoton-npcm750.dtsi"
> +
> +/ {
> + model = "Nuvoton npcm750 Development Board (Device Tree)";
> + compatible = "nuvoton,npcm750";
> +
> + chosen {
> + stdout-path = &serial3;
> + };
> +
> + memory {
> + reg = <0 0x40000000>;
> + };
> +};
> +
> +&serial0 {
> + status = "okay";
> +};
> +
> +&serial1 {
> + status = "okay";
> +};
> +
> +&serial2 {
> + status = "okay";
> +};
> +
> +&serial3 {
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
> new file mode 100644
> index 000000000000..839e45cfd695
> --- /dev/null
> +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi
> @@ -0,0 +1,165 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018 Nuvoton Technology corporation.
> +// Copyright 2018 Google, Inc.
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&gic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + enable-method = "nuvoton,npcm750-smp";
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + clocks = <&clk 10>;
> + clock-names = "clk_cpu";
> + reg = <0>;
> + next-level-cache = <&l2>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + clocks = <&clk 10>;
> + clock-names = "clk_cpu";
> + reg = <1>;
> + next-level-cache = <&l2>;
> + };
> + };
> +
> + /* external clock signal rg1refck, supplied by the phy */
> + clk-rg1refck {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + /* external clock signal rg2refck, supplied by the phy */
> + clk-rg2refck {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + clk-xin {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
> + ranges = <0x0 0xf0000000 0x00900000>;
> +
> + gcr: gcr@...000 {
> + compatible = "nuvoton,npcm750-gcr", "syscon",
> + "simple-mfd";
> + reg = <0x800000 0x1000>;
> + };
> +
> + scu: scu@...000 {
> + compatible = "arm,cortex-a9-scu";
> + reg = <0x3fe000 0x1000>;
> + };
> +
> + l2: cache-controller@...000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x3fc000 0x1000>;
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + cache-unified;
> + cache-level = <2>;
> + clocks = <&clk 22>;
> + arm,shared-override;
> + };
> +
> + gic: interrupt-controller@...000 {
> + compatible = "arm,cortex-a9-gic";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x3ff000 0x1000>,
> + <0x3fe100 0x100>;
> + };
> +
> + timer@...600 {
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0x3fe600 0x20>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + clocks = <&clk 15>;
> + };
> + };
> +
> + ahb {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
> + ranges;
> +
> + clk: clock-controller@...01000 {
> + compatible = "nuvoton,npcm750-clk";
> + #clock-cells = <1>;
> + reg = <0xf0801000 0x1000>;
> + };
> +
> + apb {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + interrupt-parent = <&gic>;
> + ranges = <0x0 0xf0000000 0x00300000>;
> +
> + timer0: timer@...0 {
> + compatible = "nuvoton,npcm750-timer";
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x8000 0x1000>;
> + clocks = <&clk 15>;
> + };
> +
> + serial0: serial@...0 {
> + compatible = "ns16550a";
> + reg = <0x1000 0x1000>;
> + clocks = <&clk 14>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + serial1: serial@...0 {
> + compatible = "ns16550a";
> + reg = <0x2000 0x1000>;
> + clocks = <&clk 14>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + serial2: serial@...0 {
> + compatible = "ns16550a";
> + reg = <0x3000 0x1000>;
> + clocks = <&clk 14>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> +
> + serial3: serial@...0 {
> + compatible = "ns16550a";
> + reg = <0x4000 0x1000>;
> + clocks = <&clk 14>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + status = "disabled";
> + };
> + };
> + };
> +};
> --
> 2.16.1.291.g4437f3f132-goog
>
Thanks,
Tomer
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