linux-kernel - Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on multi-pci-segment arches

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Date:   Tue, 13 Mar 2018 13:15:52 -0400
From:   "Liang, Kan" <kan.liang@...ux.intel.com>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     "Kroening, Gary" <gary.kroening@....com>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "hpa@...or.com" <hpa@...or.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "peterz@...radead.org" <peterz@...radead.org>,
        "Travis, Mike" <mike.travis@....com>,
        "Banman, Andrew" <abanman@....com>,
        "Sivanich, Dimitri" <dimitri.sivanich@....com>,
        "Anderson, Russ" <russ.anderson@....com>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/1] x86/platform/x86: Fix count of CHas on
 multi-pci-segment arches



On 3/13/2018 12:00 PM, Andy Shevchenko wrote:
> On Tue, Mar 13, 2018 at 5:58 PM, Andy Shevchenko
> <andy.shevchenko@...il.com> wrote:
>> On Tue, Mar 13, 2018 at 3:42 AM, Liang, Kan <kan.liang@...ux.intel.com> wrote:
>>
>>> +#define SKX_CAPID6             0x9c
> 
>>> +       pci_read_config_dword(dev, SKX_CAPID6, &val);
> 
> Moreover, this is too non-flexible. Can't you find a capability based
> on CAP ID  + offset?
> 

It looks it doesn't use capability.

16:1e.3 System peripheral: Intel Corporation Sky Lake-E PCU Registers 
(rev 04)
00: 86 80 83 20 00 00 00 00 04 00 80 08 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Thanks,
Kan