linux-kernel - Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for A53 and A57

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Date:   Thu, 15 Mar 2018 15:10:42 +0000
From:   Mark Rutland <mark.rutland@....com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     York Sun <york.sun@....com>, linux-edac@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH RFC 1/2] drivers/edac: Add L1 and L2 error detection for
 A53 and A57

On Thu, Mar 15, 2018 at 02:07:28AM +0100, Borislav Petkov wrote:
> On Wed, Mar 14, 2018 at 05:17:46PM -0700, York Sun wrote:
> > Add error detection for A53 and A57 cores. Hardware error injection
> > is supported on A53. Software error injection is supported on both.
> > For hardware error injection on A53 to work, proper access to
> > L2ACTLR_EL1, CPUACTLR_EL1 needs to be granted by EL3 firmware. This
> > is done by making an SMC call in the driver. Failure to enable access
> > disables hardware error injection. For error interrupt to work,
> > another SMC call enables access to L2ECTLR_EL1. Failure to enable
> > access disables interrupt for error reporting.
> > 
> > Signed-off-by: York Sun <york.sun@....com>
> > ---
> >  .../devicetree/bindings/edac/cortex-arm64-edac.txt |  37 +
> >  arch/arm64/include/asm/cacheflush.h                |   1 +
> >  arch/arm64/mm/cache.S                              |  35 +
> >  drivers/edac/Kconfig                               |   6 +
> >  drivers/edac/Makefile                              |   1 +
> >  drivers/edac/cortex_arm64_l1_l2.c                  | 741 +++++++++++++++++++++
> 
> I don't want per-functional unit EDAC drivers. Also, what happened to
> talking to ARM people about designing a generic ARM64 EDAC driver?

Practically speaking, a generic drivers is only possible on ARMv8.2
parts where RAS functionality is architected.

On other parts, it's IMPLEMENTATION DEFINED, and varies wildly between
CPU implementations, even if they sometimes look deceptively similar at
first glance...

This driver is certainly not generic, and is specific to Cortex-A53 and
Cortex-A57 as integrated by NXP (since it relies on NXP-specific
firmware interfaces).

Thanks,
Mark.