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Message-ID: <152149550590.242365.4351197683136837416@swboyd.mtv.corp.google.com>
Date: Mon, 19 Mar 2018 14:38:25 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Matthias Brugger <matthias.bgg@...il.com>,
Mike Turquette <mturquette@...libre.com>,
Rob Herring <robh@...nel.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Weiyi Lu <weiyi.lu@...iatek.com>
Cc: James Liao <jamesjj.liao@...iatek.com>,
Fan Chen <fan.chen@...iatek.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
srv_heupstream@...iatek.com, Weiyi Lu <weiyi.lu@...iatek.com>
Subject: Re: [PATCH v2 5/5] clk: mediatek: update clock driver of MT2712
Quoting Weiyi Lu (2018-03-12 00:03:42)
> According to ECO design change,
> 1. add new clock mux data and change some
> 2. add new clock gate data and clock factor data
> 3. change status register offset of infra subsystem
>
> Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> ---
Applied to clk-next
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