linux-kernel - Re: [PATCH v2 1/4] clk: qcom: Clear hardware clock control bit of RCG

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Message-ID: <152150012178.254778.7302484360542115877@swboyd.mtv.corp.google.com>
Date:   Mon, 19 Mar 2018 15:55:21 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Amit Nischal <anischal@...eaurora.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>
Cc:     Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Odelu Kukatla <okukatla@...eaurora.org>,
        Taniya Das <tdas@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Amit Nischal <anischal@...eaurora.org>
Subject: Re: [PATCH v2 1/4] clk: qcom: Clear hardware clock control bit of RCG

Quoting Amit Nischal (2018-03-07 23:18:12)
> For upcoming targets like sdm845, POR value of the hardware clock control
> bit is set for most of root clocks which needs to be cleared for software
> to be able to control. For older targets like MSM8996, this bit is reserved
> bit and having POR value as 0 so this patch will work for the older targets
> too. So update the configuration mask to take care of the same to clear
> hardware clock control bit.
> 
> Signed-off-by: Amit Nischal <anischal@...eaurora.org>
> ---
>  drivers/clk/qcom/clk-rcg2.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index bbeaf9c..e63db10 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -1,5 +1,5 @@
>  /*
> - * Copyright (c) 2013, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.

It would be nice if lawyers over there could avoid forcing copyright
date updates when less than half the file changes.

>   *
>   * This software is licensed under the terms of the GNU General Public
>   * License version 2, as published by the Free Software Foundation, and
> @@ -42,6 +42,7 @@
>  #define CFG_MODE_SHIFT         12
>  #define CFG_MODE_MASK          (0x3 << CFG_MODE_SHIFT)
>  #define CFG_MODE_DUAL_EDGE     (0x2 << CFG_MODE_SHIFT)
> +#define CFG_HW_CLK_CTRL_MASK   BIT(20)
> 
>  #define M_REG                  0x8
>  #define N_REG                  0xc
> @@ -276,7 +277,7 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
>         }
> 
>         mask = BIT(rcg->hid_width) - 1;
> -       mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
> +       mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
>         cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
>         cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
>         if (rcg->mnd_width && f->n && (f->m != f->n))

Is there going to be a future patch to update the RCGs to indicate they
support hardware control or not?