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Message-ID: <37D7C6CF3E00A74B8858931C1DB2F0775385655B@SHSMSX103.ccr.corp.intel.com>
Date: Mon, 19 Mar 2018 13:00:09 +0000
From: "Liang, Kan" <kan.liang@...el.com>
To: 'Peter Zijlstra' <peterz@...radead.org>
CC: "tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"acme@...nel.org" <acme@...nel.org>,
"eranian@...gle.com" <eranian@...gle.com>,
"ak@...ux.intel.com" <ak@...ux.intel.com>
Subject: RE: [PATCH V6 5/8] perf/x86/intel/uncore: add infrastructure for
free running counter
> On Thu, Jan 25, 2018 at 12:13:45PM -0800, kan.liang@...el.com wrote:
> > @@ -512,6 +538,17 @@ static int uncore_pmu_event_add(struct
> perf_event *event, int flags)
> > if (!box)
> > return -ENODEV;
> >
> > + /*
> > + * The free funning counter is assigned in event_init().
> > + * The free running counter event and free running counter
> > + * are 1:1 mapped. It doesn't need to be tracked in event_list.
> > + */
> > + if (uncore_pmc_freerunning(hwc->idx)) {
> > + if (flags & PERF_EF_START)
> > + uncore_pmu_event_start(event, 0);
> > + return 0;
> > + }
> > +
> > ret = n = uncore_collect_events(box, event, false);
> > if (ret < 0)
> > return ret;
>
> This will result in some (probably) unexpected scheduling artifacts.
> Probably the only way to really cure that is to have the free running
> counters in their own PMU and not share with the GP counters of this
> box.
I'm not quite sure what the unexpected scheduling artifacts could be.
But, yes, I can move all the free running counters to new PMU for SKX
and later platforms.
Thanks,
Kan
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