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Message-Id: <b95c4daeaf169ef0b3b689214c7c4ab37d946949.1521469118.git.rahul.lakkireddy@chelsio.com>
Date: Mon, 19 Mar 2018 19:50:36 +0530
From: Rahul Lakkireddy <rahul.lakkireddy@...lsio.com>
To: x86@...nel.org, linux-kernel@...r.kernel.org,
netdev@...r.kernel.org
Cc: tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
davem@...emloft.net, akpm@...ux-foundation.org,
torvalds@...ux-foundation.org, ganeshgr@...lsio.com,
nirranjan@...lsio.com, indranil@...lsio.com,
Rahul Lakkireddy <rahul.lakkireddy@...lsio.com>
Subject: [RFC PATCH 3/3] cxgb4: read on-chip memory 256-bits at a time
Use readqq() to read on-chip memory 256-bits at a time.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@...lsio.com>
Signed-off-by: Ganesh Goudar <ganeshgr@...lsio.com>
---
drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c | 16 ++++++++--------
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 6 ++++++
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
index 9da6f57901a9..3a319b16c8a3 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c
@@ -885,7 +885,7 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
struct adapter *adap = pdbg_init->adap;
u32 pos, offset, resid;
u32 *res_buf;
- u64 *buf;
+ u256 *buf;
int ret;
/* Argument sanity checks ...
@@ -893,10 +893,10 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
return -EINVAL;
- buf = (u64 *)hbuf;
+ buf = (u256 *)hbuf;
- /* Try to do 64-bit reads. Residual will be handled later. */
- resid = len & 0x7;
+ /* Try to do 256-bit reads. Residual will be handled later. */
+ resid = len & 0x1f;
len -= resid;
ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
@@ -917,10 +917,10 @@ static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
/* Transfer data from the adapter */
while (len > 0) {
- *buf++ = le64_to_cpu((__force __le64)
- t4_read_reg64(adap, mem_base + offset));
- offset += sizeof(u64);
- len -= sizeof(u64);
+ *buf++ = le256_to_cpu((__force __le256)
+ t4_read_reg256(adap, mem_base + offset));
+ offset += sizeof(u256);
+ len -= sizeof(u256);
/* If we've reached the end of our current window aperture,
* move the PCI-E Memory Window on to the next.
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index a5c0a649f3c7..0035ed0a2ec9 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -51,6 +51,7 @@
#include <linux/ptp_clock_kernel.h>
#include <linux/ptp_classify.h>
#include <asm/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include "t4_chip_type.h"
#include "cxgb4_uld.h"
@@ -1234,6 +1235,11 @@ static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
return readq(adap->regs + reg_addr);
}
+static inline u256 t4_read_reg256(struct adapter *adap, u32 reg_addr)
+{
+ return readqq(adap->regs + reg_addr);
+}
+
static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
{
writeq(val, adap->regs + reg_addr);
--
2.14.1
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