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Message-ID: <152156547084.183971.9281090286646445572@swboyd.mtv.corp.google.com>
Date: Tue, 20 Mar 2018 10:04:30 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: David Lechner <david@...hnology.com>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org
Cc: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Sekhar Nori <nsekhar@...com>,
Kevin Hilman <khilman@...nel.org>,
Bartosz Golaszewski <bgolaszewski@...libre.com>,
Adam Ford <aford173@...il.com>, linux-kernel@...r.kernel.org,
David Lechner <david@...hnology.com>
Subject: Re: [PATCH v8 19/42] clk: davinci: cfgchip: Add TI DA8XX USB PHY clocks
Quoting David Lechner (2018-03-15 19:52:35)
> This adds a new driver for the USB PHY clocks in the CFGCHIP2 syscon
> register on TI DA8XX-type SoCs.
>
> The USB0 (USB 2.0) PHY clock is an interesting case because it calls
> clk_enable() in a reentrant way. The USB 2.0 PSC only has to be enabled
> temporarily while we are locking the PLL, which takes place during the
> clk_enable() callback.
>
> Signed-off-by: David Lechner <david@...hnology.com>
> ---
Applied to clk-next
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