linux-kernel - Re: [PATCH v4 22/22] arm64: Add work around for Arm Cortex-A55 Erratum 1024718

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Message-ID: <d701a5ec-d8fe-3fe0-bb1f-20968403bf6a@arm.com>
Date:   Thu, 22 Mar 2018 16:42:14 +0000
From:   Suzuki K Poulose <Suzuki.Poulose@....com>
To:     Dave Martin <Dave.Martin@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, mark.rutland@....com,
        ckadabi@...eaurora.org, ard.biesheuvel@...aro.org,
        marc.zyngier@....com, catalin.marinas@....com, will.deacon@....com,
        linux-kernel@...r.kernel.org, jnair@...iumnetworks.com,
        robin.murphy@....com, shankerd@...eaurora.org
Subject: Re: [PATCH v4 22/22] arm64: Add work around for Arm Cortex-A55
 Erratum 1024718

On 21/03/18 15:31, Dave Martin wrote:
> On Tue, Mar 13, 2018 at 11:51:20AM +0000, Suzuki K Poulose wrote:
>> Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
>> from an erratum 1024718, which causes incorrect updates when DBM/AP
>> bits in a page table entry is modified without a break-before-make
>> sequence. The work around is to skip enabling the hardware DBM feature
>> on the affected cores. The hardware Access Flag management features
>> is not affected. There are some other cores suffering from this
>> errata, which could be added to the midr_list to trigger the work
>> around.
>>
>> Cc: Catalin Marinas <catalin.marinas@....com>
>> Cc: ckadabi@...eaurora.org
>> Cc: Dave Martin <dave.martin@....com>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@....com>
> 
> [...]
> 
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 4e73c610a409..0fc097e2b72e 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -963,9 +963,23 @@ static inline void __cpu_enable_hw_dbm(void)
>>   	isb();
>>   }
>>   
>> +static bool cpu_has_broken_dbm(void)
>> +{
>> +	/* List of CPUs which have broken DBM support. */
>> +	static const struct midr_range cpus[] = {
>> +#ifdef CONFIG_ARM64_ERRATUM_1024718
>> +		MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
>> +#endif
>> +		{},
>> +	};
>> +
>> +	return is_midr_in_range_list(read_cpuid_id(), cpus);
>> +}
>> +
>>   static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
>>   {
>> -	return has_cpuid_feature(cap, SCOPE_LOCAL_CPU);
>> +	return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
>> +	       !cpu_has_broken_dbm();
> 
> This refactoring seems sensbile to me.  The mapping between erratum IDs
> and features that don't work is never guaranteed to be 1:1, so it
> makes sense for the check function to have a generic name and to paste
> in the relevant erratum ID ranges depending on the kernel config.
> 

Thanks Dave. Apologies for the lost change log for the patch. It looked
like this (before it was lost in a rebase :-()


Changes since v3:
  - Renamed cpu_has_erratum_1024718() to cpu_has_broken_dbm() to
    allow for different CPU Errata configs to share a single routine
    for black listing CPUs. Dropped Dave's Reviewed-by


> [...]
> 
> Reviewed-by: Dave Martin <Dave.Martin@....com>

Cheers
Suzuki