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Message-ID: <BY2PR1201MB09833C062294345C829E90A9C8A90@BY2PR1201MB0983.namprd12.prod.outlook.com>
Date: Thu, 22 Mar 2018 22:02:52 +0000
From: Casey Leedom <leedom@...lsio.com>
To: Sinan Kaya <okaya@...eaurora.org>, Jason Gunthorpe <jgg@...pe.ca>
CC: SWise OGC <swise@...ngridcomputing.com>,
'kbuild test robot' <lkp@...el.com>,
"kbuild-all@...org" <kbuild-all@...org>,
"linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
"timur@...eaurora.org" <timur@...eaurora.org>,
"sulrich@...eaurora.org" <sulrich@...eaurora.org>,
"linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Steve Wise <swise@...lsio.com>,
"'Doug Ledford'" <dledford@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Michael Werner <werner@...lsio.com>
Subject: Re: [PATCH v4 4/6] infiniband: cxgb4: Eliminate duplicate barriers on
weakly-ordered archs
Okay, thanks Sinan. I ~think~ we're on the same page here.
Our guy Michael Werner is carefully going through our drivers with Steve
Wise. I'd like to let them work on the changes with a lot of thought and
testing before diving in too far.
We had thought that we could get around the lack of a real Relaxed
Ordering Write on the PowerPC via the __raw_write*() API, but that isn't
really part of the defined API and various platforms define that API
differently (some doing PCI Byte Ordering rearrangements and some not). I
think that we're going to have to work with the PowerPC platform folks to
get a real Relaxed Ordering Write.
Casey
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