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Message-ID: <6cb618e9-0aa0-ba54-b556-d7a6823913d7@gmail.com>
Date: Fri, 23 Mar 2018 14:46:38 -0700
From: Florian Fainelli <f.fainelli@...il.com>
To: Alexandre Belloni <alexandre.belloni@...tlin.com>,
"David S . Miller" <davem@...emloft.net>
Cc: Allan Nielsen <Allan.Nielsen@...rosemi.com>,
razvan.stefanescu@....com, po.liu@....com,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Andrew Lunn <andrew@...n.ch>, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mips@...ux-mips.org, Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH net-next 2/8] dt-bindings: net: add DT bindings for
Microsemi MIIM
On 03/23/2018 01:11 PM, Alexandre Belloni wrote:
> DT bindings for the Microsemi MII Management Controller found on Microsemi
> SoCs
>
> Cc: Rob Herring <robh+dt@...nel.org>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@...tlin.com>
> ---
> .../devicetree/bindings/net/mscc-miim.txt | 25 ++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/mscc-miim.txt
>
> diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt
> new file mode 100644
> index 000000000000..711ac9ab853c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt
> @@ -0,0 +1,25 @@
> +Microsemi MII Management Controller (MIIM) / MDIO
> +=================================================
> +
> +Properties:
> +- compatible: must be "mscc,ocelot-miim"
> +- reg: The base address of the MDIO bus controller register bank. Optionally, a
> + second register bank can be defined if there is an associated reset register
> + for internal PHYs
> +- #address-cells: Must be <1>.
> +- #size-cells: Must be <0>. MDIO addresses have no size component.
Missing interrupt property documentation (sorry), other than that:
Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
--
Florian
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