linux-kernel - Re: [PATCH] Fixes in TI QSPI driver to allow more than one flash chip

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Message-ID: <496c162d-5e3c-e008-a14b-6b990e253e64@ti.com>
Date:   Tue, 27 Mar 2018 09:30:11 +0530
From:   Vignesh R <vigneshr@...com>
To:     "Kwiatkowski, Arkadiusz" <arkadiusz.kwiatkowski@...iv.com>,
        "broonie@...nel.org" <broonie@...nel.org>
CC:     "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] Fixes in TI QSPI driver to allow more than one flash chip



On Thursday 22 March 2018 06:03 PM, Kwiatkowski, Arkadiusz wrote:
> Add checking for which SPI device was memory-mapped to allow more than
> one flash device being used on QSPI bus. Fix parameters order in
> regmap_update_bits calls.
> 
> Signed-off-by: Arkadiusz Kwiatkowski <arkadiusz.kwiatkowski@...iv.com>
> ---

Thanks for the patch! Fixes are legitimate but,
Your mailer has grabbled the patch (especially white spaces). Please use
git send-email to send patches.
Run scripts/checkpatch.pl --strict on the patch for kernel coding style
checks.
Please look at git log drivers/spi/spi-ti-qspi.c and fix up $subject
accordingly. Split this patch into two: One fixing up
regmap_update_bits() call and other fixing up mmap setup for more than
one CS.


>  drivers/spi/spi-ti-qspi.c | 22 +++++++++++++---------
>  1 file changed, 13 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
> index c24d9b4..3d1dc4f 100644
> --- a/drivers/spi/spi-ti-qspi.c
> +++ b/drivers/spi/spi-ti-qspi.c
> @@ -66,7 +66,7 @@ struct ti_qspi {
>  u32 cmd;
>  u32 dc;
> 
> -bool mmap_enabled;
> +struct spi_device*mmap_spi_device;
>  };
> 
>  #define QSPI_PID(0x0)
> @@ -490,10 +490,10 @@ static void ti_qspi_enable_memory_map(struct
> spi_device *spi)
>  ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
>  if (qspi->ctrl_base) {
>  regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
> -   MEM_CS_EN(spi->chip_select),
> -   MEM_CS_MASK);
> +   MEM_CS_MASK,
> +   MEM_CS_EN(spi->chip_select));
>  }
> -qspi->mmap_enabled = true;
> +qspi->mmap_spi_device = spi;
>  }
> 
>  static void ti_qspi_disable_memory_map(struct spi_device *spi)
> @@ -503,8 +503,8 @@ static void ti_qspi_disable_memory_map(struct
> spi_device *spi)
>  ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
>  if (qspi->ctrl_base)
>  regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
> -   0, MEM_CS_MASK);
> -qspi->mmap_enabled = false;
> +   MEM_CS_MASK, 0);
> +qspi->mmap_spi_device = NULL;
>  }
> 
>  static void ti_qspi_setup_mmap_read(struct spi_device *spi,
> @@ -544,8 +544,12 @@ static int ti_qspi_spi_flash_read(struct spi_device
> *spi,
> 
>  mutex_lock(&qspi->list_lock);
> 
> -if (!qspi->mmap_enabled)
> +if (qspi->mmap_spi_device != spi) {
> +if (qspi->mmap_spi_device != NULL)
> +ti_qspi_disable_memory_map(qspi->mmap_spi_device);
>  ti_qspi_enable_memory_map(spi);
> +}
> +
>  ti_qspi_setup_mmap_read(spi, msg);
> 
>  if (qspi->rx_chan) {
> @@ -600,7 +604,7 @@ static int ti_qspi_start_transfer_one(struct
> spi_master *master,
> 
>  mutex_lock(&qspi->list_lock);
> 
> -if (qspi->mmap_enabled)
> +if (qspi->mmap_spi_device != NULL)
>  ti_qspi_disable_memory_map(spi);
> 
>  list_for_each_entry(t, &m->transfers, transfer_list) {
> @@ -787,7 +791,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
>  master->spi_flash_read = NULL;
>  }
>  }
> -qspi->mmap_enabled = false;
> +qspi->mmap_spi_device = NULL;
> 
>  ret = devm_spi_register_master(&pdev->dev, master);
>  if (!ret)
> --
> 2.7.4
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-- 
Regards
Vignesh