linux-kernel - [PATCH 5/8] PCI: dwc: designware: Define maximum number of vectors

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Message-Id: <a0930afdf1a0953d0e8b66c999ce8923be517a03.1522235224.git.gustavo.pimentel@synopsys.com>
Date:   Wed, 28 Mar 2018 12:38:35 +0100
From:   Gustavo Pimentel <gustavo.pimentel@...opsys.com>
To:     bhelgaas@...gle.com, lorenzo.pieralisi@....com,
        Joao.Pinto@...opsys.com, jingoohan1@...il.com, kishon@...com,
        robh+dt@...nel.org, mark.rutland@....com
Cc:     linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, gustavo.pimentel@...opsys.com
Subject: [PATCH 5/8] PCI: dwc: designware: Define maximum number of vectors

Adds a callback that defines the maximum number of vectors that can be use
by the Root Complex.

Since this is a parameter associated to each SoC IP setting, makes sense to
be configurable and easily visible to future modifications.

The designware IP supports a maximum of 256 vectors.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@...opsys.com>
---
 drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index 921ab07..11271bb 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp)
 	return 0;
 }
 
+static void dw_plat_set_num_vectors(struct pcie_port *pp)
+{
+	pp->num_vectors = MAX_MSI_IRQS;
+}
+
 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
 	.host_init = dw_plat_pcie_host_init,
+	.set_num_vectors = dw_plat_set_num_vectors,
 };
 
 static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
-- 
2.7.4