linux-kernel - [PATCH v3 2/3] ARM64: dts: meson-axg: add an 32K alt aoclk

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Message-ID: <20180328030130.240336-3-yixun.lan@amlogic.com>
Date:   Wed, 28 Mar 2018 11:01:29 +0800
From:   Yixun Lan <yixun.lan@...ogic.com>
To:     Kevin Hilman <khilman@...libre.com>
CC:     Yixun Lan <yixun.lan@...ogic.com>, Carlo Caione <carlo@...one.org>,
        Rob Herring <robh@...nel.org>,
        Qiufang Dai <qiufang.dai@...ogic.com>,
        <linux-amlogic@...ts.infradead.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: [PATCH v3 2/3] ARM64: dts: meson-axg: add an 32K alt aoclk

The ao_clk81 in AO domain have two clock source,
one from a 32K alt crystal we name it as ao_alt_clk,
another is the clk81 signal from EE domain.

Acked-by: Jerome Brunet <jbrunet@...libre.com>
Signed-off-by: Yixun Lan <yixun.lan@...ogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b0eff7d7f771..40ca49fb94a6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -108,6 +108,13 @@
 		#clock-cells = <0>;
 	};
 
+	ao_alt_xtal: ao_alt_xtal-clk {
+		compatible = "fixed-clock";
+		clock-frequency = <32000000>;
+		clock-output-names = "ao_alt_xtal";
+		#clock-cells = <0>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
2.15.1