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Date:   Wed, 4 Apr 2018 16:09:07 +0000
From:   Nadav Amit <namit@...are.com>
To:     Dave Hansen <dave.hansen@...ux.intel.com>
CC:     LKML <linux-kernel@...r.kernel.org>,
        "open list:MEMORY MANAGEMENT" <linux-mm@...ck.org>,
        Andrea Arcangeli <aarcange@...hat.com>,
        Andy Lutomirski <luto@...nel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        "keescook@...gle.com" <keescook@...gle.com>,
        Hugh Dickins <hughd@...gle.com>,
        Juergen Gross <jgross@...e.com>,
        "x86@...nel.org" <x86@...nel.org>
Subject: Re: [PATCH 09/11] x86/pti: enable global pages for shared areas

Dave Hansen <dave.hansen@...ux.intel.com> wrote:

> On 04/03/2018 09:45 PM, Nadav Amit wrote:
>> Dave Hansen <dave.hansen@...ux.intel.com> wrote:
>> 
>>> From: Dave Hansen <dave.hansen@...ux.intel.com>
>>> 
>>> The entry/exit text and cpu_entry_area are mapped into userspace and
>>> the kernel.  But, they are not _PAGE_GLOBAL.  This creates unnecessary
>>> TLB misses.
>>> 
>>> Add the _PAGE_GLOBAL flag for these areas.
>>> 
>>> Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com>
>>> Cc: Andrea Arcangeli <aarcange@...hat.com>
>>> Cc: Andy Lutomirski <luto@...nel.org>
>>> Cc: Linus Torvalds <torvalds@...ux-foundation.org>
>>> Cc: Kees Cook <keescook@...gle.com>
>>> Cc: Hugh Dickins <hughd@...gle.com>
>>> Cc: Juergen Gross <jgross@...e.com>
>>> Cc: x86@...nel.org
>>> Cc: Nadav Amit <namit@...are.com>
>>> ---
>>> 
>>> b/arch/x86/mm/cpu_entry_area.c |   10 +++++++++-
>>> b/arch/x86/mm/pti.c            |   14 +++++++++++++-
>>> 2 files changed, 22 insertions(+), 2 deletions(-)
>>> 
>>> diff -puN arch/x86/mm/cpu_entry_area.c~kpti-why-no-global arch/x86/mm/cpu_entry_area.c
>>> --- a/arch/x86/mm/cpu_entry_area.c~kpti-why-no-global	2018-04-02 16:41:17.157605167 -0700
>>> +++ b/arch/x86/mm/cpu_entry_area.c	2018-04-02 16:41:17.162605167 -0700
>>> @@ -27,8 +27,16 @@ EXPORT_SYMBOL(get_cpu_entry_area);
>>> void cea_set_pte(void *cea_vaddr, phys_addr_t pa, pgprot_t flags)
>>> {
>>> 	unsigned long va = (unsigned long) cea_vaddr;
>>> +	pte_t pte = pfn_pte(pa >> PAGE_SHIFT, flags);
>>> 
>>> -	set_pte_vaddr(va, pfn_pte(pa >> PAGE_SHIFT, flags));
>>> +	/*
>>> +	 * The cpu_entry_area is shared between the user and kernel
>>> +	 * page tables.  All of its ptes can safely be global.
>>> +	 */
>>> +	if (boot_cpu_has(X86_FEATURE_PGE))
>>> +		pte = pte_set_flags(pte, _PAGE_GLOBAL);
>> 
>> I think it would be safer to check that the PTE is indeed present before
>> setting _PAGE_GLOBAL. For example, percpu_setup_debug_store() sets PAGE_NONE
>> for non-present entries. In this case, since PAGE_NONE and PAGE_GLOBAL use
>> the same bit, everything would be fine, but it might cause bugs one day.
> 
> That's a reasonable safety thing to add, I think.
> 
> But, looking at it, I am wondering why we did this in
> percpu_setup_debug_store():
> 
>        for (; npages; npages--, cea += PAGE_SIZE)
>                cea_set_pte(cea, 0, PAGE_NONE);
> 
> Did we really want that to be PAGE_NONE, or was it supposed to create a
> PTE that returns true for pte_none()?

I yield it to others to answer...

> 
>>> /*
>>> +		 * Setting 'target_pmd' below creates a mapping in both
>>> +		 * the user and kernel page tables.  It is effectively
>>> +		 * global, so set it as global in both copies.  Note:
>>> +		 * the X86_FEATURE_PGE check is not _required_ because
>>> +		 * the CPU ignores _PAGE_GLOBAL when PGE is not
>>> +		 * supported.  The check keeps consistentency with
>>> +		 * code that only set this bit when supported.
>>> +		 */
>>> +		if (boot_cpu_has(X86_FEATURE_PGE))
>>> +			*pmd = pmd_set_flags(*pmd, _PAGE_GLOBAL);
>> 
>> Same here.
> 
> Is there  a reason that the pmd_none() check above this does not work?

For any practical reasons, right now, it should be fine. But pmd_none() will
not save us if _PAGE_PROTNONE ever changes, for example. Note that the check
is with pmd_none() and not pmd_protnone().

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