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Message-ID: <20180412125250.to46vdgztwa2jsbq@tardis>
Date:   Thu, 12 Apr 2018 20:52:50 +0800
From:   Boqun Feng <boqun.feng@...il.com>
To:     Paolo Bonzini <pbonzini@...hat.com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
        linux-kernel@...r.kernel.org,
        Alan Stern <stern@...land.harvard.edu>,
        Andrea Parri <parri.andrea@...il.com>,
        Will Deacon <will.deacon@....com>,
        Nicholas Piggin <npiggin@...il.com>,
        David Howells <dhowells@...hat.com>,
        Jade Alglave <j.alglave@....ac.uk>,
        Luc Maranget <luc.maranget@...ia.fr>,
        Akira Yokosawa <akiyks@...il.com>
Subject: Re: [PATCH] memory-model: fix cheat sheet typo

On Wed, Apr 11, 2018 at 07:06:36PM +0200, Paolo Bonzini wrote:
> On 11/04/2018 18:31, Peter Zijlstra wrote:
> >>>                                    Prior Operation   Subsequent Operation
> >>>                                    ---------------   ---------------------
> >>>                                    R  W  RMW  SV     R  W  DR  DW  RMW  SV
> >>>                                    -  -  ---  --     -  -  --  --  ---  --
> >>> smp_store_mb()                     Y  Y    Y   Y      Y  Y   Y   Y   Y   Y
> > I'm not sure about that, the generic version of that reads:
> > 
> > include/asm-generic/barrier.h:#define __smp_store_mb(var, value)
> >     do { WRITE_ONCE(var, value); __smp_mb(); } while (0)
> > 
> > Which doesn't not have an smp_mb() before, so it doesn't actually order
> > prior; or I'm failing to read the table wrong.
> 
> You're not, even better reason to document it. :)  I was going from
> memory for the x86 version.
> 
> I'll start tomorrow on fixes to the current document, while we discuss
> the split format and what to do about cumulativity and propagation.
> 

Besides, since smp_store_mb() is a store, so there is no DR or DW for
the subsequent operations I think, because dependencies come from a read
rather than a write.

Regards,
Boqun

> Paolo

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