linux-kernel - [RFC 2/3] ARM: dts: Renesas RZ/N1D SMP enable method

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Message-Id: <1523871304-48517-4-git-send-email-michel.pollet@bp.renesas.com>
Date:   Mon, 16 Apr 2018 10:34:58 +0100
From:   Michel Pollet <michel.pollet@...renesas.com>
To:     linux-renesas-soc@...r.kernel.org,
        Simon Horman <horms@...ge.net.au>
Cc:     phil.edworthy@...esas.com, buserror+upstream@...il.com,
        Michel Pollet <michel.pollet@...renesas.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Magnus Damm <magnus.damm@...il.com>,
        Russell King <linux@...linux.org.uk>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Maxime Ripard <maxime.ripard@...tlin.com>,
        Andy Gross <andy.gross@...aro.org>,
        Florian Fainelli <f.fainelli@...il.com>,
        Andreas Färber <afaerber@...e.de>,
        Juri Lelli <juri.lelli@....com>,
        Carlo Caione <carlo@...lessm.com>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Frank Rowand <frank.rowand@...y.com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: [RFC 2/3] ARM: dts: Renesas RZ/N1D SMP enable method

Add a special enable method for the second CA7 of the Renesas RZ/N1D
(R9A06G032), as well as the default value for the "cpu-release-addr"
property.

Signed-off-by: Michel Pollet <michel.pollet@...renesas.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 7d84b38..50f3043d 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -33,6 +33,8 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a7";
 			reg = <1>;
+			enable-method = "renesas,r9a06g032-smp";
+			cpu-release-addr = <0x4000c204>;
 		};
 	};
 
-- 
2.7.4