linux-kernel - Re: [PATCH] clk: mediatek: correct the clocks for MT2701 HDMI PHY module

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Message-ID: <152389649546.51482.15378110712126175925@swboyd.mtv.corp.google.com>
Date:   Mon, 16 Apr 2018 09:34:55 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Ryder Lee <ryder.lee@...iatek.com>
Cc:     Matthias Brugger <matthias.bgg@...il.com>,
        chunhui dai <chunhui.dai@...iatek.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        Ryder Lee <ryder.lee@...iatek.com>
Subject: Re: [PATCH] clk: mediatek: correct the clocks for MT2701 HDMI PHY module

Quoting Ryder Lee (2018-04-15 19:31:58)
> The hdmitx_dig_cts clock signal is not a child of clk26m,
> and the actual output of the PLL block is derived from
> the tvdpll via a configurable PLL post-divider.
> 
> It is used as the PLL reference input to the HDMI PHY module.
> 
> Signed-off-by: Chunhui Dai <chunhui.dai@...iatek.com>
> Signed-off-by: Ryder Lee <ryder.lee@...iatek.com>

Any sort of Fixes: tag here?