lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Mon, 16 Apr 2018 19:57:43 +0200 From: Jerome Brunet <jbrunet@...libre.com> To: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Russell King <linux@...linux.org.uk> Cc: Jerome Brunet <jbrunet@...libre.com>, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH 3/3] clk: mux: add duty cycle passthrough ops A clock mux does not resample the clock signal, it give the same signal as the selected parent, so it can use the duty cycle passthrough operations. Signed-off-by: Jerome Brunet <jbrunet@...libre.com> --- drivers/clk/clk-mux.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 1628b93655ed..f7c597779928 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -124,11 +124,15 @@ const struct clk_ops clk_mux_ops = { .get_parent = clk_mux_get_parent, .set_parent = clk_mux_set_parent, .determine_rate = clk_mux_determine_rate, + .set_duty_cycle = __clk_set_duty_cycle_passthrough, + .get_duty_cycle = __clk_get_duty_cycle_passthrough, }; EXPORT_SYMBOL_GPL(clk_mux_ops); const struct clk_ops clk_mux_ro_ops = { .get_parent = clk_mux_get_parent, + .set_duty_cycle = __clk_set_duty_cycle_passthrough, + .get_duty_cycle = __clk_get_duty_cycle_passthrough, }; EXPORT_SYMBOL_GPL(clk_mux_ro_ops); -- 2.14.3
Powered by blists - more mailing lists