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Message-ID: <CAJ2AOiP1-TnSRdrLxowQ7DqzxoBYENfbO1ZR5A0_kwzLJ0WztA@mail.gmail.com>
Date: Tue, 17 Apr 2018 13:35:27 -0700
From: Alex Solomatnikov <sols@...ive.com>
To: Alan Kao <alankao@...estech.com>
Cc: Palmer Dabbelt <palmer@...ive.com>, Albert Ou <albert@...ive.com>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...hat.com>,
Namhyung Kim <namhyung@...nel.org>,
Jonathan Corbet <corbet@....net>,
linux-riscv@...ts.infradead.org, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org, Nick Hu <nickhu@...estech.com>,
Greentime Hu <greentime@...estech.com>
Subject: Re: [PATCH v3 1/2] perf: riscv: preliminary RISC-V support
On Tue, Apr 17, 2018 at 1:38 AM, Alan Kao <alankao@...estech.com> wrote:
> +static inline void write_counter(int idx, u64 value)
> +{
> + /* currently not supported */
> +}
CSR writes can be emulated: https://github.com/riscv/riscv-pk/pull/98
Or at least write_counter() should have BUG() or WARN_ONCE() or
something like that.
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