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Message-Id: <a71f296a31b14009e2db9608280102a0fa56b1d8.1523973931.git.gustavo.pimentel@synopsys.com>
Date: Tue, 17 Apr 2018 15:34:25 +0100
From: Gustavo Pimentel <gustavo.pimentel@...opsys.com>
To: bhelgaas@...gle.com, lorenzo.pieralisi@....com,
Joao.Pinto@...opsys.com, jingoohan1@...il.com, kishon@...com,
robh+dt@...nel.org, mark.rutland@....com
Cc: linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, gustavo.pimentel@...opsys.com
Subject: [PATCH v5 07/10] PCI: dwc: Define maximum number of vectors
Adds a callback that defines the maximum number of vectors that can be use
by the Root Complex.
Since this is a parameter associated to each SoC IP setting, makes sense to
be configurable and easily visible to future modifications.
The designware IP supports a maximum of 256 vectors.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@...opsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.
Changes v3->v4:
- Nothing changed, just to follow the patch set version.
Changes v4->v5:
- Nothing changed, just to follow the patch set version.
drivers/pci/dwc/pcie-designware-plat.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index efc315c..5937fed 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -48,8 +48,14 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp)
return 0;
}
+static void dw_plat_set_num_vectors(struct pcie_port *pp)
+{
+ pp->num_vectors = MAX_MSI_IRQS;
+}
+
static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
.host_init = dw_plat_pcie_host_init,
+ .set_num_vectors = dw_plat_set_num_vectors,
};
static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
--
2.7.4
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