lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAOMZO5C9GxqVJWB18j7JQ+3D93eL1r_PG5woxmOc=8cZRdVX=w@mail.gmail.com>
Date:   Thu, 19 Apr 2018 19:15:26 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Stefan Agner <stefan@...er.ch>
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Uwe Kleine-König 
        <u.kleine-koenig@...gutronix.de>, Jiri Slaby <jslaby@...e.com>,
        linux-serial@...r.kernel.org,
        linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

On Mon, Apr 16, 2018 at 12:35 PM, Stefan Agner <stefan@...er.ch> wrote:
> To reset the UART the SRST needs be cleared (low active). According
> to the documentation the bit will remain active for 4 module clocks
> until it is cleared (set to 1).
>
> Hence the real register need to be read in case the cached register
> indcates that the SRST bit is zero.

s/indcates/indicates

> This bug lead to wrong baudrate because the baud rate register got
> restored before reset completed in imx_flush_buffer.
>
> Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR")
> Signed-off-by: Stefan Agner <stefan@...er.ch>

Reviewed-by: Fabio Estevam <fabio.estevam@....com>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ