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Message-ID: <tip-d7717587ac6deae00e0b66c0113a046be2c6fb1c@git.kernel.org>
Date:   Fri, 20 Apr 2018 03:43:15 -0700
From:   tip-bot for Stephane Eranian <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, mingo@...nel.org, hpa@...or.com,
        kan.liang@...el.com, eranian@...gle.com,
        linux-kernel@...r.kernel.org, peterz@...radead.org
Subject: [tip:perf/urgent] perf/x86/intel/uncore: Revert "Remove SBOX
 support for Broadwell server"

Commit-ID:  d7717587ac6deae00e0b66c0113a046be2c6fb1c
Gitweb:     https://git.kernel.org/tip/d7717587ac6deae00e0b66c0113a046be2c6fb1c
Author:     Stephane Eranian <eranian@...gle.com>
AuthorDate: Fri, 23 Mar 2018 09:11:29 -0400
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Fri, 20 Apr 2018 12:41:17 +0200

perf/x86/intel/uncore: Revert "Remove SBOX support for Broadwell server"

This reverts commit 3b94a891667c ("perf/x86/intel/uncore: Remove
SBOX support for Broadwell server")

Revert because there exists a proper workaround for Broadwell-EP servers
without SBOX now. Note that BDX-DE does not have a SBOX.

Signed-off-by: Stephane Eranian <eranian@...gle.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Kan Liang <kan.liang@...el.com>
Acked-by: Peter Zijlstra <peterz@...radead.org>
Cc: ak@...ux.intel.com
Cc: osk@...gle.com
Cc: mark@...dzero.net
Link: https://lkml.kernel.org/r/1521810690-2576-1-git-send-email-kan.liang@linux.intel.com

---
 arch/x86/events/intel/uncore_snbep.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index c98b943e58b4..5bbbbee11879 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -3028,10 +3028,27 @@ static struct intel_uncore_type bdx_uncore_cbox = {
 	.format_group		= &hswep_uncore_cbox_format_group,
 };
 
+static struct intel_uncore_type bdx_uncore_sbox = {
+	.name			= "sbox",
+	.num_counters		= 4,
+	.num_boxes		= 4,
+	.perf_ctr_bits		= 48,
+	.event_ctl		= HSWEP_S0_MSR_PMON_CTL0,
+	.perf_ctr		= HSWEP_S0_MSR_PMON_CTR0,
+	.event_mask		= HSWEP_S_MSR_PMON_RAW_EVENT_MASK,
+	.box_ctl		= HSWEP_S0_MSR_PMON_BOX_CTL,
+	.msr_offset		= HSWEP_SBOX_MSR_OFFSET,
+	.ops			= &hswep_uncore_sbox_msr_ops,
+	.format_group		= &hswep_uncore_sbox_format_group,
+};
+
+#define BDX_MSR_UNCORE_SBOX	3
+
 static struct intel_uncore_type *bdx_msr_uncores[] = {
 	&bdx_uncore_ubox,
 	&bdx_uncore_cbox,
 	&hswep_uncore_pcu,
+	&bdx_uncore_sbox,
 	NULL,
 };
 
@@ -3047,6 +3064,10 @@ void bdx_uncore_cpu_init(void)
 		bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
 	uncore_msr_uncores = bdx_msr_uncores;
 
+	/* BDX-DE doesn't have SBOX */
+	if (boot_cpu_data.x86_model == 86)
+		uncore_msr_uncores[BDX_MSR_UNCORE_SBOX] = NULL;
+
 	hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints;
 }
 

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