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Message-Id: <20180423105003.9004-15-enric.balletbo@collabora.com>
Date: Mon, 23 Apr 2018 12:49:50 +0200
From: Enric Balletbo i Serra <enric.balletbo@...labora.com>
To: architt@...eaurora.org, inki.dae@...sung.com,
thierry.reding@...il.com, hjc@...k-chips.com,
seanpaul@...omium.org, airlied@...ux.ie, tfiga@...omium.org,
heiko@...ech.de
Cc: dri-devel@...ts.freedesktop.org, dianders@...omium.org,
a.hajda@...sung.com, kernel@...labora.com,
m.szyprowski@...sung.com, linux-samsung-soc@...r.kernel.org,
jy0922.shim@...sung.com, rydberg@...math.org, krzk@...nel.org,
linux-rockchip@...ts.infradead.org, kgene@...nel.org,
orjan.eide@....com, wxt@...k-chips.com, jeffy.chen@...k-chips.com,
linux-arm-kernel@...ts.infradead.org, wzz@...k-chips.com,
hl@...k-chips.com, jingoohan1@...il.com, sw0312.kim@...sung.com,
linux-kernel@...r.kernel.org, kyungmin.park@...sung.com,
Laurent.pinchart@...asonboard.com, kuankuan.y@...il.com,
hshi@...omium.org,
Enric Balletbo i Serra <enric.balletbo@...labora.com>
Subject: [RESEND PATCH v6 14/27] drm/bridge: analogix_dp: Don't use ANALOGIX_DP_PLL_CTL to control pll
From: zain wang <wzz@...k-chips.com>
There is no register named ANALOGIX_DP_PLL_CTL in Rockchip edp phy reg
list. We should use BIT_4 in ANALOGIX_DP_PD to control the pll power
instead of ANALOGIX_DP_PLL_CTL.
Cc: Douglas Anderson <dianders@...omium.org>
Signed-off-by: zain wang <wzz@...k-chips.com>
Signed-off-by: Sean Paul <seanpaul@...omium.org>
Signed-off-by: Thierry Escande <thierry.escande@...labora.com>
Reviewed-by: Andrzej Hajda <a.hajda@...sung.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
Tested-by: Marek Szyprowski <m.szyprowski@...sung.com>
Reviewed-by: Archit Taneja <architt@...eaurora.org>
---
.../gpu/drm/bridge/analogix/analogix_dp_reg.c | 20 +++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 7b7fd227e1f9..02ab1aaa9993 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -230,16 +230,20 @@ enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
{
u32 reg;
+ u32 mask = DP_PLL_PD;
+ u32 pd_addr = ANALOGIX_DP_PLL_CTL;
- if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
- reg |= DP_PLL_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
- } else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
- reg &= ~DP_PLL_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
+ if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
+ pd_addr = ANALOGIX_DP_PD;
+ mask = RK_PLL_PD;
}
+
+ reg = readl(dp->reg_base + pd_addr);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ writel(reg, dp->reg_base + pd_addr);
}
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
--
2.17.0
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