linux-kernel - [PATCH v1 1/2] ARM: dts: stm32: add ltdc support on stm32mp157c

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <1524556488-5404-2-git-send-email-yannick.fertre@st.com>
Date:   Tue, 24 Apr 2018 09:54:47 +0200
From:   yannick fertre <yannick.fertre@...com>
To:     Philippe Cornu <philippe.cornu@...com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Loic Pallardy <loic.pallardy@...com>,
        "Gerald Baeza" <gerald.baeza@...com>,
        Patrice Chotard <patrice.chotard@...com>,
        "Kamel Kholti" <kamel.kholti@...com>
CC:     Benjamin Gaignard <benjamin.gaignard@...com>
Subject: [PATCH v1 1/2] ARM: dts: stm32: add ltdc support on stm32mp157c

Add support for the display controller ltdc.

Signed-off-by: yannick fertre <yannick.fertre@...com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..af6cc48 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/reset/stm32mp1-resets.h>
 
 / {
 	#address-cells = <1>;
@@ -167,6 +168,17 @@
 			#reset-cells = <1>;
 		};
 
+		ltdc: display-controller@...01000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x5a001000 0x400>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rcc LTDC_PX>;
+			clock-names = "lcd";
+			resets = <&rcc LTDC_R>;
+			status = "disabled";
+		};
+
 		usart1: serial@...00000 {
 			compatible = "st,stm32h7-uart";
 			reg = <0x5c000000 0x400>;
-- 
1.9.1