linux-kernel - Re: [PATCH v1 0/4] Restore ULPI USB on Tegra20

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Message-ID: <20180430112804.GA5770@ulmo>
Date:   Mon, 30 Apr 2018 13:28:04 +0200
From:   Thierry Reding <thierry.reding@...il.com>
To:     Dmitry Osipenko <digetx@...il.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Linus Walleij <linus.walleij@...aro.org>
Cc:     Jonathan Hunter <jonathanh@...dia.com>,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Marcel Ziswiler <marcel@...wiler.com>,
        Marc Dietrich <marvin24@....de>, linux-clk@...r.kernel.org,
        linux-gpio@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1 0/4] Restore ULPI USB on Tegra20

On Mon, Apr 30, 2018 at 11:48:21AM +0200, Thierry Reding wrote:
> On Fri, Apr 27, 2018 at 02:58:14AM +0300, Dmitry Osipenko wrote:
> > Hello,
> > 
> > This series of patches fixes ULPI USB on Tegra20. The original problem
> > was reported by Marcel Ziswiler, he found that "ulpi-link" clock was
> > incorrectly set to CDEV2 instead of PLL_P_OUT4. Marcel made a patch
> > that changed the "ulpi-link" clock to PLL_P_OUT4 and that fixed issue
> > with the USB for the devices that have CDEV2 being enabled by bootloader.
> > The patch got into the kernel and later Marc Dietrich found that USB
> > stopped working on the "paz00" Tegra20 board. After a bit of discussion
> > was revealed that PLL_P_OUT4 is the parent clock of the CDEV2 and clock
> > driver was setting CDEV2's parent incorrectly. The parent clock is actually
> > determined by the pinmuxing config of CDEV2 pingroup. This patchset fixes
> > the parent of CDEV2 clock by making Tegra's pinctrl driver a clock provider,
> > providing CDEV1/2 clock muxes (thanks to Peter De Schrijver for the
> > suggestion), and then setting these clock muxes as parents for the CDEV1/2
> > clocks. In the end Marcel's CDEV2->PLL_P_OUT4 change is reverted since CDEV2
> > (aka MCLK2) is the actual clock source for "ulpi-link".
> > 
> > Dmitry Osipenko (4):
> >   clk: tegra20: Add DEV1/DEV2 OSC dividers
> >   pinctrl: tegra20: Provide CDEV1/2 clock muxes
> >   clk: tegra20: Set correct parents for CDEV1/2 clocks
> >   ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20"
> > 
> >  arch/arm/boot/dts/tegra20.dtsi          |  2 +-
> >  drivers/clk/tegra/clk-tegra20.c         | 18 +++++++++++----
> >  drivers/pinctrl/tegra/pinctrl-tegra.c   | 11 ---------
> >  drivers/pinctrl/tegra/pinctrl-tegra.h   | 11 +++++++++
> >  drivers/pinctrl/tegra/pinctrl-tegra20.c | 30 ++++++++++++++++++++++++-
> >  5 files changed, 55 insertions(+), 17 deletions(-)
> 
> Stephen, Michael, Linus,
> 
> as far as I can tell there aren't any build dependencies between the
> above, so technically these could all be merged through the individual
> trees. There's a runtime dependency from patch 2 on patch 1 and from
> patch 3 on patch 2, though I don't think they will cause any actual
> failures at runtime.
> 
> But I can also pick this up into the Tegra tree and send out pull
> requests to you for v4.18 (at around v4.17-rc6), if that's what you
> prefer.

Marc just pointed out to me on IRC that this fixes a regression that was
introduced in v4.17-rc1.

Can you guys pick this up into your -fixes branches? Again, I volunteer
to collect these into a separate branch and submit via ARM SoC (the DTS
patch is crucial in enabling the fix) with your Acked-bys if that's the
preferred option.

Thierry

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