[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <alpine.DEB.2.21.1804302151530.1596@nanos.tec.linutronix.de>
Date: Mon, 30 Apr 2018 21:53:25 +0200 (CEST)
From: Thomas Gleixner <tglx@...utronix.de>
To: Jörg Otte <jrg.otte@...il.com>
cc: kirill.shutemov@...ux.intel.com,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linus Torvalds <torvalds@...ux-foundation.org>,
Borislav Petkov <bp@...en8.de>
Subject: Re: [v4.17-rcx] Lost IBPB, IBRS_FW support for spectre_v2
mitigation.
Jörg,
On Mon, 30 Apr 2018, Jörg Otte wrote:
> In v4.16 I already had support for BPB, IBRS_FW for spectre_v2 mitigation.
> But this went away in v17-rcx.
>
> With 4.16 I have:
> jojo@...hte:~$ cd /sys/devices/system/cpu/vulnerabilities; grep ".*" *
> meltdown:Mitigation: PTI
> spectre_v1:Mitigation: __user pointer sanitization
> spectre_v2:Mitigation: Full generic retpoline, IBPB, IBRS_FW
>
> With 4.17-rcx I have:
> meltdown:Mitigation: PTI
> spectre_v1:Mitigation: __user pointer sanitization
> spectre_v2:Mitigation: Full generic retpoline
>
> Processor is
> vendor_id : GenuineIntel
> cpu family : 6
> model : 60
> model name : Intel(R) Core(TM) i5-4200M CPU @ 2.50GHz
> stepping : 3
> microcode : 0x24
>
>
> The problem goes away if I revert:
> d94a155 x86/cpu: Prevent cpuinfo_x86::x86_phys_bits adjustment corruption
Does the patch below fix the problem for you?
Thanks,
tglx
8<------------------
Subject: x86/cpu: Restore CPUID_8000_0008_EBX reload
From: Thomas Gleixner <tglx@...utronix.de>
Date: Mon, 30 Apr 2018 21:47:46 +0200
The recent commt which addresses the x86_phys_bits corruption with
encrypted memory on CPUID reload after a microcode update lost the reload
of CPUID_8000_0008_EBX as well.
As a consequence IBRS and IBRS_FW are not longer detected
Restore the behaviour by bringing the reload of CPUID_8000_0008_EBX back,.
Fixes: d94a155c59c9 ("x86/cpu: Prevent cpuinfo_x86::x86_phys_bits adjustment corruption")
Reported-by: Jörg Otte <jrg.otte@...il.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: kirill.shutemov@...ux.intel.com
---
arch/x86/kernel/cpu/common.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -848,6 +848,11 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
c->x86_power = edx;
}
+ if (c->extended_cpuid_level >= 0x80000008) {
+ cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
+ c->x86_capability[CPUID_8000_0008_EBX] = ebx;
+ }
+
if (c->extended_cpuid_level >= 0x8000000a)
c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
Powered by blists - more mailing lists