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Message-ID: <20180503213645.20694-3-yixun.lan@amlogic.com>
Date: Thu, 3 May 2018 21:36:43 +0000
From: Yixun Lan <yixun.lan@...ogic.com>
To: Mark Brown <broonie@...nel.org>
CC: Sunny Luo <sunny.luo@...ogic.com>,
Yixun Lan <yixun.lan@...ogic.com>,
Neil Armstrong <narmstrong@...libre.com>,
Jerome Brunet <jbrunet@...libre.com>,
Kevin Hilman <khilman@...libre.com>,
Carlo Caione <carlo@...one.org>, <linux-spi@...r.kernel.org>,
<linux-amlogic@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH 2/3] spi: meson-axg: enhance output enable feature
From: Sunny Luo <sunny.luo@...ogic.com>
The SPICC controller in Meson-AXG is capable of driving the CLK/MOSI/SS
signal lines through the idle state (between two transmission operation),
which avoid the signals floating in unexpected state.
Signed-off-by: Sunny Luo <sunny.luo@...ogic.com>
Signed-off-by: Yixun Lan <yixun.lan@...ogic.com>
---
drivers/spi/spi-meson-spicc.c | 28 ++++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 8489f4c9f465..90b15f7d50dd 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -115,6 +115,13 @@
#define SPICC_DWADDR 0x24 /* Write Address of DMA */
+#define SPICC_ENH_CTL0 0x38 /* Enhanced Feature */
+#define SPICC_ENH_MOSI_OEN BIT(25)
+#define SPICC_ENH_CLK_OEN BIT(26)
+#define SPICC_ENH_CS_OEN BIT(27)
+#define SPICC_ENH_CLK_CS_DELAY_EN BIT(28)
+#define SPICC_ENH_MAIN_CLK_AO BIT(29)
+
#define writel_bits_relaxed(mask, val, addr) \
writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr)
@@ -123,6 +130,7 @@
struct meson_spicc_data {
unsigned int max_speed_hz;
+ bool has_oen;
};
struct meson_spicc_device {
@@ -145,6 +153,19 @@ struct meson_spicc_device {
bool is_last_burst;
};
+static void meson_spicc_oen_enable(struct meson_spicc_device *spicc)
+{
+ u32 conf;
+
+ if (!spicc->data->has_oen)
+ return;
+
+ conf = readl_relaxed(spicc->base + SPICC_ENH_CTL0) |
+ SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN;
+
+ writel_relaxed(conf, spicc->base + SPICC_ENH_CTL0);
+}
+
static inline bool meson_spicc_txfull(struct meson_spicc_device *spicc)
{
return !!FIELD_GET(SPICC_TF,
@@ -453,6 +474,8 @@ static int meson_spicc_prepare_message(struct spi_master *master,
writel_bits_relaxed(BIT(24), BIT(24), spicc->base + SPICC_TESTREG);
+ meson_spicc_oen_enable(spicc);
+
return 0;
}
@@ -605,11 +628,12 @@ static int meson_spicc_remove(struct platform_device *pdev)
}
static const struct meson_spicc_data meson_spicc_gx_data = {
- .max_speed_hz = 30000000,
+ .max_speed_hz = 30000000,
};
static const struct meson_spicc_data meson_spicc_axg_data = {
- .max_speed_hz = 80000000,
+ .max_speed_hz = 80000000,
+ .has_oen = true,
};
static const struct of_device_id meson_spicc_of_match[] = {
--
2.17.0
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