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Message-ID: <20180503171410.q52ak27u47gycy6o@flea>
Date: Thu, 3 May 2018 19:14:10 +0200
From: Maxime Ripard <maxime.ripard@...tlin.com>
To: Yong Deng <yong.deng@...ewell.com>
Cc: Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Chen-Yu Tsai <wens@...e.org>,
"David S. Miller" <davem@...emloft.net>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Linus Walleij <linus.walleij@...aro.org>,
Randy Dunlap <rdunlap@...radead.org>,
Hans Verkuil <hans.verkuil@...co.com>,
Stanimir Varbanov <stanimir.varbanov@...aro.org>,
Benjamin Gaignard <benjamin.gaignard@...aro.org>,
Arnd Bergmann <arnd@...db.de>,
Philipp Zabel <p.zabel@...gutronix.de>,
Ramesh Shanmugasundaram <ramesh.shanmugasundaram@...renesas.com>,
Yannick Fertre <yannick.fertre@...com>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Todor Tomov <todor.tomov@...aro.org>,
linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-sunxi@...glegroups.com
Subject: Re: [PATCH v9 0/2] Initial Allwinner V3s CSI Support
Hi Yong,
On Tue, Mar 06, 2018 at 09:51:10AM +0800, Yong Deng wrote:
> This patchset add initial support for Allwinner V3s CSI.
>
> Allwinner V3s SoC features two CSI module. CSI0 is used for MIPI CSI-2
> interface and CSI1 is used for parallel interface. This is not
> documented in datasheet but by test and guess.
>
> This patchset implement a v4l2 framework driver and add a binding
> documentation for it.
>
> Currently, the driver only support the parallel interface. And has been
> tested with a BT1120 signal which generating from FPGA. The following
> fetures are not support with this patchset:
> - ISP
> - MIPI-CSI2
> - Master clock for camera sensor
> - Power regulator for the front end IC
Do you plan on sending another version some time soon? It would be
awesome to have this in 4.18.
Thanks!
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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