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Message-ID: <CAD=FV=WNa=k__pymaTWEGtHn+QaHW7ezPb+ZsO4Z9UtLKYQQSg@mail.gmail.com>
Date: Fri, 4 May 2018 12:46:51 -0700
From: Doug Anderson <dianders@...omium.org>
To: Manu Gautam <mgautam@...eaurora.org>
Cc: Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
devicetree@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>,
Evan Green <evgreen@...omium.org>,
Vivek Gautam <vivek.gautam@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-usb@...r.kernel.org
Subject: Re: [PATCH v5 1/7] clk: msm8996-gcc: Mark halt check as no-op for
USB/PCIE pipe_clk
Hi,
On Wed, May 2, 2018 at 2:06 PM, Manu Gautam <mgautam@...eaurora.org> wrote:
> The USB and PCIE pipe clocks are sourced from external clocks
> inside the QMP USB/PCIE PHYs. Enabling or disabling of PIPE RCG
> clocks is dependent on PHY initialization sequence hence
> update halt_check to BRANCH_HALT_SKIP for these clocks so
> that clock status bit is not polled when enabling or disabling
> the clocks. It allows to simplify PHY client driver code which
> is both user and source of the pipe_clk and avoid error logging
> related status check on clk_disable/enable.
>
> Signed-off-by: Manu Gautam <mgautam@...eaurora.org>
> ---
> drivers/clk/qcom/gcc-msm8996.c | 4 ++++
> 1 file changed, 4 insertions(+)
FWIW this matches my understanding of what Stephen and you agreed upon. Thus:
Reviewed-by: Douglas Anderson <dianders@...omium.org>
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