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Message-ID: <ebe8d8aa-ea7d-62ad-106e-abb0db95edce@ti.com>
Date: Sun, 6 May 2018 20:43:30 +0530
From: Sekhar Nori <nsekhar@...com>
To: David Lechner <david@...hnology.com>, <linux-clk@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
CC: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: davinci: pll-dm355: fix SYSCLKn parent names
Hi David,
On Friday 04 May 2018 07:54 PM, David Lechner wrote:
> This fixes the parent clock names of the SYSCLKn clocks for the DM355
> SoC in the TI DaVinici PLL clock driver.
>
> It appears that this name just didn't get updated to the correct name
> like the other SoCs during the driver's development.
>
> Reported-by: Sekhar Nori <nsekhar@...com>
> Signed-off-by: David Lechner <david@...hnology.com>
> ---
>
> Sekhar, can you please test to make sure this works?
>
>
> drivers/clk/davinci/pll-dm355.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c
> index a0cff4212ac3..13dc6b8ea97a 100644
> --- a/drivers/clk/davinci/pll-dm355.c
> +++ b/drivers/clk/davinci/pll-dm355.c
> @@ -22,10 +22,10 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
> PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
> };
>
> -SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> -SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> -SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
> -SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
>
> int dm355_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
> {
> @@ -62,8 +62,8 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
> PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
> };
>
> -SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
> -SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV);
We also need SYSCLK_ALWAYS_ENABLED for PLL2 sysclk1. With that change, I
was able to boot DM355 EVM and the clock tree looks good too.
> +SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
>
> int dm355_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
> {
Regards,
Sekhar
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