linux-kernel - Re: [PATCH v2 05/17] arm64: Helper for parange to PASize

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Message-ID: <89d5f41c-56e1-9195-ec08-05a708bf15f0@arm.com>
Date:   Tue, 8 May 2018 14:47:03 +0100
From:   Suzuki K Poulose <Suzuki.Poulose@....com>
To:     James Morse <james.morse@....com>
Cc:     linux-arm-kernel@...ts.infradead.org, ard.biesheuvel@...aro.org,
        kvm@...r.kernel.org, marc.zyngier@....com, catalin.marinas@....com,
        punit.agrawal@....com, will.deacon@....com,
        linux-kernel@...r.kernel.org, kristina.martsenko@....com,
        pbonzini@...hat.com, kvmarm@...ts.cs.columbia.edu
Subject: Re: [PATCH v2 05/17] arm64: Helper for parange to PASize

On 03/05/18 15:39, James Morse wrote:
> Hi Suzuki,
> 
> Nit: KVM in the subject line?

Well, the helper is generic and its just that KVM makes use of it.

> 
> On 27/03/18 14:15, Suzuki K Poulose wrote:
>> Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
>> size shift. Limit the size to the maximum supported by the kernel.
>> We are about to move the user of this code and this helps to
>> keep the changes cleaner.
> 
>> diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
>> index fbf0aab..1f2a5dd 100644
>> --- a/arch/arm64/include/asm/cpufeature.h
>> +++ b/arch/arm64/include/asm/cpufeature.h
>> @@ -311,6 +311,22 @@ static inline u64 read_zcr_features(void)
>>   	return zcr;
>>   }
>>   
>> +static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
>> +{
>> +	switch (parange) {
>> +	case 0: return 32;
>> +	case 1: return 36;
>> +	case 2: return 40;
>> +	case 3: return 42;
>> +	case 4: return 44;
>> +	/* Report 48 bit if the kernel doesn't support 52bit */
>> +	default:
>> +	case 5: return 48;
>> +#ifdef CONFIG_ARM64_PA_BITS_52
>> +	case 6: return 52;
>> +#endif
> 
> Eeew. I thought 'default' had to appear at the end of the list, but evidently
> not! If the last three bit value ever gets used this is going to look really weird.

I could rearrange them a bit to :

	case 4: ..
#ifdef CONFIG_ARM64_PA_BITS_52
	case 6: ...
#endif
	case 5:
	/* Report 48 bit if the kernel doesn't support 52bit */
	default: return 48;

> 
> Can't we have a helper that just does the mapping, then apply the clamping with
> something like:
> | parange = min(CONFIG_ARM64_PA_BITS, parange);

Yes, I think that might be a bit cleaner.

> 
> 
> Its odd that the helper has the id-register in the name, but expects you do the
> shift and mask for it...
> 
> (and for this patch, KVM has already done the 52bit clamping with:
> | 	if (parange > ID_AA64MMFR0_PARANGE_MAX)
> |		parange = ID_AA64MMFR0_PARANGE_MAX;
> )
> 

As mentioned in the other thread, I will change the name of the helper.

> 
>> diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c
>> index 603e1ee..b1129c8 100644
>> --- a/arch/arm64/kvm/hyp/s2-setup.c
>> +++ b/arch/arm64/kvm/hyp/s2-setup.c
>> @@ -19,11 +19,13 @@
>>   #include <asm/kvm_arm.h>
>>   #include <asm/kvm_asm.h>
>>   #include <asm/kvm_hyp.h>
>> +#include <asm/cpufeature.h>
>>   
>>   u32 __hyp_text __init_stage2_translation(void)
>>   {
> 
> Nit: Why change the variable you put this in, if its all removed again in patch 11?

The parange holds the PARange initially, used to set the VTCR.IPS and is then
overloaded with the converted "phys-shift". The change is a minor cleanup to
make that clear, even though we remove it later as we don't deal with the
phys-shifts anymore. I would prefer to keep it as it is.

Cheers
Suzuki