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Message-Id: <20180510184751.13416-1-paul@crapouillou.net>
Date: Thu, 10 May 2018 20:47:44 +0200
From: Paul Cercueil <paul@...pouillou.net>
To: Guenter Roeck <linux@...ck-us.net>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Ralf Baechle <ralf@...ux-mips.org>,
James Hogan <jhogan@...nel.org>
Cc: Wim Van Sebroeck <wim@...ux-watchdog.org>,
Mathieu Malaterre <malat@...ian.org>,
linux-watchdog@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-mips@...ux-mips.org,
Paul Cercueil <paul@...pouillou.net>
Subject: [PATCH v3 1/8] watchdog: JZ4740: Disable clock after stopping counter
Previously, the clock was disabled first, which makes the watchdog
component insensitive to register writes.
Signed-off-by: Paul Cercueil <paul@...pouillou.net>
Reviewed-by: Guenter Roeck <linux@...ck-us.net>
---
drivers/watchdog/jz4740_wdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
v2: No change
v3: No change
diff --git a/drivers/watchdog/jz4740_wdt.c b/drivers/watchdog/jz4740_wdt.c
index aafbeb96561b..55c9a1f26498 100644
--- a/drivers/watchdog/jz4740_wdt.c
+++ b/drivers/watchdog/jz4740_wdt.c
@@ -124,8 +124,8 @@ static int jz4740_wdt_stop(struct watchdog_device *wdt_dev)
{
struct jz4740_wdt_drvdata *drvdata = watchdog_get_drvdata(wdt_dev);
- jz4740_timer_disable_watchdog();
writeb(0x0, drvdata->base + JZ_REG_WDT_COUNTER_ENABLE);
+ jz4740_timer_disable_watchdog();
return 0;
}
--
2.11.0
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