linux-kernel - [PATCH v9 08/12] arm64: Add support for ACPI based firmware tables

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Date:   Fri, 11 May 2018 18:58:03 -0500
From:   Jeremy Linton <jeremy.linton@....com>
To:     linux-acpi@...r.kernel.org
Cc:     Sudeep.Holla@....com, linux-arm-kernel@...ts.infradead.org,
        Lorenzo.Pieralisi@....com, hanjun.guo@...aro.org,
        rjw@...ysocki.net, Will.Deacon@....com, Catalin.Marinas@....com,
        gregkh@...uxfoundation.org, Mark.Rutland@....com,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
        wangxiongfeng2@...wei.com, vkilari@...eaurora.org, ahs3@...hat.com,
        Dietmar.Eggemann@....com, Morten.Rasmussen@....com,
        palmer@...ive.com, lenb@...nel.org, john.garry@...wei.com,
        austinwc@...eaurora.org, tnowicki@...iumnetworks.com,
        jhugo@...eaurora.org, ard.biesheuvel@...aro.org,
        Jeremy Linton <jeremy.linton@....com>
Subject: [PATCH v9 08/12] arm64: Add support for ACPI based firmware tables

The /sys cache entries should support ACPI/PPTT generated cache
topology information.  For arm64, if ACPI is enabled, determine
the max number of cache levels and populate them using the PPTT
table if one is available.

Signed-off-by: Jeremy Linton <jeremy.linton@....com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@...aro.org>
Tested-by: Vijaya Kumar K <vkilari@...eaurora.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@...wei.com>
Tested-by: Tomasz Nowicki <Tomasz.Nowicki@...ium.com>
Reviewed-by: Sudeep Holla <sudeep.holla@....com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@...aro.org>
---
 arch/arm64/kernel/cacheinfo.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
index 380f2e2fbed5..0bf0a835122f 100644
--- a/arch/arm64/kernel/cacheinfo.c
+++ b/arch/arm64/kernel/cacheinfo.c
@@ -17,6 +17,7 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+#include <linux/acpi.h>
 #include <linux/cacheinfo.h>
 #include <linux/of.h>
 
@@ -46,7 +47,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf,
 
 static int __init_cache_level(unsigned int cpu)
 {
-	unsigned int ctype, level, leaves, of_level;
+	unsigned int ctype, level, leaves, fw_level;
 	struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
 
 	for (level = 1, leaves = 0; level <= MAX_CACHE_LEVEL; level++) {
@@ -59,15 +60,19 @@ static int __init_cache_level(unsigned int cpu)
 		leaves += (ctype == CACHE_TYPE_SEPARATE) ? 2 : 1;
 	}
 
-	of_level = of_find_last_cache_level(cpu);
-	if (level < of_level) {
+	if (acpi_disabled)
+		fw_level = of_find_last_cache_level(cpu);
+	else
+		fw_level = acpi_find_last_cache_level(cpu);
+
+	if (level < fw_level) {
 		/*
 		 * some external caches not specified in CLIDR_EL1
 		 * the information may be available in the device tree
 		 * only unified external caches are considered here
 		 */
-		leaves += (of_level - level);
-		level = of_level;
+		leaves += (fw_level - level);
+		level = fw_level;
 	}
 
 	this_cpu_ci->num_levels = level;
-- 
2.13.6