linux-kernel - Re: [PATCH 1/2] KVM: X86: Fix CR3 reserve bits

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Message-ID: <CANRm+CxeLocYkhbw0KTCU9Ypii7NqcLMH=KwXPZxJbGDhxoiJQ@mail.gmail.com>
Date:   Sun, 13 May 2018 17:14:50 +0800
From:   Wanpeng Li <kernellwp@...il.com>
To:     Liran Alon <liran.alon@...cle.com>
Cc:     Radim Krcmar <rkrcmar@...hat.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        LKML <linux-kernel@...r.kernel.org>, kvm <kvm@...r.kernel.org>,
        Junaid Shahid <junaids@...gle.com>
Subject: Re: [PATCH 1/2] KVM: X86: Fix CR3 reserve bits

2018-05-13 17:09 GMT+08:00 Liran Alon <liran.alon@...cle.com>:
>
> ----- kernellwp@...il.com wrote:
>
>> 2018-05-13 16:28 GMT+08:00 Liran Alon <liran.alon@...cle.com>:
>> >
>> > ----- kernellwp@...il.com wrote:
>> >
>> >> 2018-05-13 15:53 GMT+08:00 Liran Alon <liran.alon@...cle.com>:
>> >> >
>> >> > ----- kernellwp@...il.com wrote:
>> >> >
>> >> >> From: Wanpeng Li <wanpengli@...cent.com>
>> >> >>
>> >> >> MSB of CR3 is a reserved bit if the PCIDE bit is not set in
>> CR4.
>> >> >> It should be checked when PCIDE bit is not set, however commit
>> >> >> 'd1cd3ce900441 ("KVM: MMU: check guest CR3 reserved bits based
>> on
>> >> >> its physical address width")' removes the bit 63 checking
>> >> >> unconditionally. This patch fixes it by checking bit 63 of CR3
>> >> >> when PCIDE bit is not set in CR4.
>> >> >>
>> >> >> Fixes: d1cd3ce900441 (KVM: MMU: check guest CR3 reserved bits
>> based
>> >> on
>> >> >> its physical address width)
>> >> >> Cc: Paolo Bonzini <pbonzini@...hat.com>
>> >> >> Cc: Radim Krčmář <rkrcmar@...hat.com>
>> >> >> Cc: Junaid Shahid <junaids@...gle.com>
>> >> >> Signed-off-by: Wanpeng Li <wanpengli@...cent.com>
>> >> >> ---
>> >> >>  arch/x86/kvm/emulate.c | 4 +++-
>> >> >>  arch/x86/kvm/x86.c     | 2 +-
>> >> >>  2 files changed, 4 insertions(+), 2 deletions(-)
>> >> >>
>> >> >> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
>> >> >> index b3705ae..b21f427 100644
>> >> >> --- a/arch/x86/kvm/emulate.c
>> >> >> +++ b/arch/x86/kvm/emulate.c
>> >> >> @@ -4189,7 +4189,9 @@ static int check_cr_write(struct
>> >> >> x86_emulate_ctxt *ctxt)
>> >> >>                               maxphyaddr = eax & 0xff;
>> >> >>                       else
>> >> >>                               maxphyaddr = 36;
>> >> >> -                     rsvd = rsvd_bits(maxphyaddr, 62);
>> >> >> +                     if (ctxt->ops->get_cr(ctxt, 4) &
>> >> X86_CR4_PCIDE)
>> >> >> +                             new_val &= ~CR3_PCID_INVD;
>> >> >> +                     rsvd = rsvd_bits(maxphyaddr, 63);
>> >> >
>> >> > I would prefer instead to do this:
>> >> > if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE)
>> >> >     rsvd &= ~CR3_PCID_INVD;
>> >> > It makes more sense as opposed to temporary removing the
>> >> CR3_PCID_INVD bit from new_val.
>> >>
>> >> It tries the same way
>> >>
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__git.kernel.org_pub_scm_virt_kvm_kvm.git_commit_-3Fid-3Dc19986fea873f3c745122bf79013a872a190f212&d=DwIFaQ&c=RoP1YumCXCgaWHvlZYR8PZh8Bv7qIrMUB65eapI_JnE&r=Jk6Q8nNzkQ6LJ6g42qARkg6ryIDGQr-yKXPNGZbpTx0&m=r52WDgKBorUHwe_B_5Nw2Le_F_E0ne8lqqWW6n-3bSg&s=ufTcXvhhAMkY3XP6gAx-HiKCT8ynPWo2fs2z9DqCzM4&e=
>> >> pointed out.
>> >>
>> >> Regards,
>> >> Wanpeng Li
>> >
>> > Yes but there it makes sense as new CR3 value should not have bit 63
>> set in vcpu->arch.cr3.
>>
>> When X86_CR4_PCIDE == 0 and CR3 63 bit is set, a #GP is missing in
>> your suggestion.
>>
>> Regards,
>> Wanpeng Li
>
> Why?
>
> I suggest the following change:
> - rsvd = rsvd_bits(maxphyaddr, 62);
> + rsvd = rsvd_bits(maxphyaddr, 63);
> + if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE)
> +     rsvd &= ~CR3_PCID_INVD;
>
> In this case, if PCIDE=0 then bit 63 is set in rsvd and therefore check_cr_write() will emulate_gp() as needed.

Ok, I misread your first reply, will send out v2.

Regards,
Wanpeng Li