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Message-Id: <20180514211610.26618-3-enric.balletbo@collabora.com>
Date:   Mon, 14 May 2018 23:16:02 +0200
From:   Enric Balletbo i Serra <enric.balletbo@...labora.com>
To:     MyungJoo Ham <myungjoo.ham@...sung.com>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Rob Herring <robh+dt@...nel.org>,
        Will Deacon <will.deacon@....com>,
        Heiko Stuebner <heiko@...ech.de>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Sandy Huang <hjc@...k-chips.com>,
        David Airlie <airlied@...ux.ie>
Cc:     linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
        Derek Basehore <dbasehore@...omium.org>,
        linux-clk@...r.kernel.org, linux-rockchip@...ts.infradead.org,
        dri-devel@...ts.freedesktop.org, Lin Huang <hl@...k-chips.com>,
        kernel@...labora.com, Sean Paul <seanpaul@...omium.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        Mark Rutland <mark.rutland@....com>
Subject: [RFC PATCH 02/10] dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle.

The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU
general register files to know the DRAM type, so add a phandle to the
syscon that manages these registers.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
---

 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
index 0ec68141f85a..951789c0cdd6 100644
--- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -12,6 +12,8 @@ Required properties:
 			 for details.
 - center-supply:	 DMC supply node.
 - status:		 Marks the node enabled/disabled.
+- rockchip,pmu:		 Phandle to the syscon managing the "PMU general register
+			 files".
 
 Optional properties:
 - interrupts:		 The CPU interrupt number. The interrupt specifier
-- 
2.17.0

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