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Message-ID: <20180514102217.uc3kzhu6gs4wapuo@um.fi.intel.com>
Date:   Mon, 14 May 2018 13:22:17 +0300
From:   Alexander Shishkin <alexander.shishkin@...ux.intel.com>
To:     Luwei Kang <luwei.kang@...el.com>
Cc:     kvm@...r.kernel.org, tglx@...utronix.de, mingo@...hat.com,
        hpa@...or.com, x86@...nel.org, chao.p.peng@...ux.intel.com,
        thomas.lendacky@....com, bp@...e.de, Kan.liang@...el.com,
        Janakarajan.Natarajan@....com, dwmw@...zon.co.uk,
        linux-kernel@...r.kernel.org, alexander.shishkin@...ux.intel.com,
        peterz@...radead.org, mathieu.poirier@...aro.org,
        kstewart@...uxfoundation.org, gregkh@...uxfoundation.org,
        pbonzini@...hat.com, rkrcmar@...hat.com, david@...hat.com,
        bsd@...hat.com, yu.c.zhang@...ux.intel.com, joro@...tes.org
Subject: Re: [PATCH v8 01/12] perf/x86/intel/pt: Move Intel-PT MSRs bit
 definitions to a public header

On Mon, May 14, 2018 at 06:57:01PM +0800, Luwei Kang wrote:
> From: Chao Peng <chao.p.peng@...ux.intel.com>
> 
> Intel Processor Trace virtualization enabling in KVM guest
> need to access these MSRs bit definitions, so move them to
> public header file msr-index.h.
> @@ -115,6 +148,7 @@
>  #define MSR_IA32_RTIT_ADDR2_B		0x00000585
>  #define MSR_IA32_RTIT_ADDR3_A		0x00000586
>  #define MSR_IA32_RTIT_ADDR3_B		0x00000587
> +#define MSR_IA32_RTIT_ADDR_RANGE	4

This one wasn't there before, so belongs in a different patch.

Regards,
--
Alex

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