linux-kernel - [RESEND PATCH 3/5] clk: tegra20: init NDFLASH clock to sensible rate

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Message-Id: <7b870e6f8ea65606d136314a34a79f63c244b13c.1526990589.git.stefan@agner.ch>
Date:   Tue, 22 May 2018 14:07:07 +0200
From:   Stefan Agner <stefan@...er.ch>
To:     boris.brezillon@...tlin.com, dwmw2@...radead.org,
        computersforpeace@...il.com, marek.vasut@...il.com,
        robh+dt@...nel.org, mark.rutland@....com, thierry.reding@...il.com,
        mturquette@...libre.com, sboyd@...nel.org
Cc:     dev@...xeye.de, miquel.raynal@...tlin.com, richard@....at,
        marcel@...wiler.com, krzk@...nel.org, digetx@...il.com,
        benjamin.lindqvist@...ian.se, jonathanh@...dia.com,
        pdeschrijver@...dia.com, pgaikwad@...dia.com, mirza.krak@...il.com,
        linux-mtd@...ts.infradead.org, linux-tegra@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, Stefan Agner <stefan@...er.ch>
Subject: [RESEND PATCH 3/5] clk: tegra20: init NDFLASH clock to sensible rate

From: Lucas Stach <dev@...xeye.de>

Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.

Signed-off-by: Lucas Stach <dev@...xeye.de>
Signed-off-by: Stefan Agner <stefan@...er.ch>
---
 drivers/clk/tegra/clk-tegra20.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 0ee56dd04cec..dff8c425cd28 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
 	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
 	{ TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
+	{ TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0 },
 	/* must be the last entry */
 	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
 };
-- 
2.17.0